Skip to Main Content

Ansys Path FX
Variability-Aware SoC Path Timing & Clock Tree Analysis Software

Ansys Path FX complements existing sign-off flows by evaluating all timing paths and clock trees in an SoC for delay and variance.

PATH AND CLOCK TIMING

Voltage Drop and Variation-Aware Path and Clock Timing Analysis

Ansys Path FX allows you to calculate timing with variation on a full SoC, without taking any shortcuts. Its unique cell modeling delivers SPICE accuracy timing for any voltage or variation condition with a single library. Path FX has a fully threaded and distributed architecture, with the ability to scale to thousands of CPUs

  • Complementary to Regular STA
    Complementary to Regular STA
  • Timing with RedHawk-SC
    Timing with RedHawk-SC
Voltage drop

Quick Specs

Ansys Path FX’s path-based timing analysis has the technology to account for all critical contributors to delay and constraints across multiple process, voltage, temperature corners and scenarios. It can also automatically identify and simulate every clock path in your design.

  • Simulate Delays, Slews and Constraints
  • Impact of Dynamic Voltage Drop on Timing
  • Transistor-Level SPICE Models
  • Multi-Corner and Multi-Scenario
  • Non-Gaussian ULV Timing
  • Simulate Thousands of Paths
  • Automatically Identify Clock Paths
  • Full Waveform Propagation
  • Multi-Threaded and Distributed
  • Analyze Electrical Overstress (EOS)
  • Read and Write Standard Files
  • All Advanced Nodes
2020-11-ansys-stock-20201123-0290-horizontal.png

Ansys Path FX’s timing analysis requires only a single library model for full voltage- and variability-aware timing analysis. Its high capacity and speed allow for greater coverage, and thus better design reliability.

Two of the biggest challenges facing successful chip design today are limiting the power consumption through lower supply voltages and managing the complexity of advanced silicon processes at 7nm and below.  Both of these trends introduce significantly more timing and performance variability on every transistor, making it difficult to ensure a design will work for all temperature, voltage and process conditions. Current voltage variability analysis requires multiple timing libraries, characterized at different voltages, with timing interpolation estimates between them.

Ansys Path FX brings a much more efficient, simple and accurate solution by using a single SPICE-based library characterization that is inherently able to include voltage variability, temperature variability, electrical overstress (EOS), clock jitter and other variables at full SPICE accuracy, without shortcuts.

Path FX has the capacity and speed to analyze thousands of critical paths and entire clock trees, to ensure comprehensive coverage and ensure a robust and reliable design that will not fail in silicon.

Applications

View all Applications
Electronics Reliability

Electronics Reliability

Learn how Ansys integrated electronics reliability tools can help you  solve your biggest thermal, electrical and mechanical reliability challenges.

Applications

High-speed and SPICE-accurate timing analysis with voltage, temperature and process variability

Ansys Path FX complements existing sign-off flows with the performance to evaluate all timing paths and clock trees in an SoC for delay and variability on even the largest designs.

Path FX’s path timing of delays and slews can automatically identify and simulate every clock path in your design. It accounts for all critical contributors to delay and constraints across multiple process, voltage, temperature corners and scenarios. Path FX leverages SPICE transistor models to create a single library characterization that uses full waveform propagation to provide SPICE accuracy and correctly analyze all variability effects with no shortcuts.

 

Key Features

High capacity SPICE-level timing and clock tree analysis using unique voltage, temperature and process variability-aware cell modeling

  • Accurate timing with IR drop
  • Single library for all voltages
  • Automatic clock tree analysis
  • Comprehensive critical path coverage
  • Complements traditional sign-off timers
  • Easy integration with standard files

Ansys Path FX simulates delays, slews and constraints. The simulator is fully statistical and handles non-gaussian behavior at low voltage and advanced process nodes. Path FX accounts for accurate multi-voltage analysis and performs accurate DvD-aware timing analysis.

Ansys Path FX simulates thousands of paths using standard cell models or transistor-level SPICE models, providing both corner and statistical timing results. Its full waveform propagation provides the accuracy needed to get reliable results at ultralow voltage and advanced processes. Miller-capacitance and other effects are handled correctly, with no shortcuts.

Ansys Path FX automatically identifies and simulates every clock path in your design.

Ansys Path FX leverages the SPICE transistor models and full waveform propagation to provide the accuracy needed to get reliable results at ultra-low voltage and on-chip variation (OCV) for advanced processes. Miller-capacitance and other effects are handled correctly, with no shortcuts.

Ansys Path FX is threaded and distributed, dramatically reducing turnaround time and memory requirements, compared to Monte Carlo SPICE.

Ansys Path FX reads industry-standard files and generates a rich set of reports and SDF for back-annotating results into your flow.

In addition to simulating timing paths, Path FX automatically identifies and simulates every clock path in your design with accurate multi-voltage analysis and clock jitter analysis.

불가능을 가능하게 만들 준비가 되셨나요?

문의하기

* = 필수 항목

문의해 주셔서 감사합니다!

We’re here to answer your questions and look forward to speaking with you. A member of our Ansys sales team will contact you shortly.

Racecars on a track