Optimizing Processor Power-to-Performance Ratios Using Early RTL Design-for-Power Methodology - Webinar
Conventional approaches for chip power-consumption analysis begin once a gate level netlist is available. At this stage, possible changes that can impact power are limited by schedule and cost considerations. AMD recently adopted ANSYS PowerArtist for a design-for-power methodology that begins early at the RTL stage, making it possible to significantly reduce power consumption on a processor design.
Learn how, through rigorous tracking of power over multiple bandwidth scenarios, AMD identified areas of significant wasted power consumption and addressed them through high-impact RTL changes. Discover how they achieved a 70 percent power reduction in the idle mode and an improvement of 400 percent in the power-bandwidth slope using ANSYS PowerArtist.