Efficient On-chip ESD Protection Design and Verification Methodology Using EDA Tools - Presentation

Due to shrinking silicon geometries, today's integrated circuits depend on robust ESD protection logic to ensure reliable performance. Engineers need to leverage simulation tools to identify potential problem areas early. In this presentation, we demonstrate how ANSYS Totem, ANSYS RedHawk and ANSYS PathFinder can be used from initial design stage to post-layout verification stage. This presentation given at the 2014 ANSYS Electronics Simulation Expo.