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Slash Power Integrity Runtimes with Chip Power Model-SC

Chip designs are growing larger, requiring precise Chip Power Models (CPM) for power integrity analysis. With 3DIC and <3nm nodes, faster, accurate model generation is crucial.

Date/Time:
January 14, 2026
9 AM PST

Venue:
Virtual

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Overview

Over the past few years, chip designs have been getting larger, with compute workloads exceeding billions of nodes.

For these designs, running power integrity analysis of the chip combined with the package/PCB requires creation of an equivalent circuit model called the Chip Power Model (CPM). The CPM captures the electrical behavior of the chip over a broad range of frequencies.

But now with the advent of 3DIC and advanced technology nodes (<3nm), it is essential that the chip power model (CPM) be generated even more quickly, without loss of accuracy.

We will share how you can leverage the latest algorithmic advances to accelerate the generation of these models through CPM-SC.

What Attendees Will Learn

  • What is a Chip Power Model
  • How to leverage the latest algorithmic advances through Chip Power Model-SC
  • Best practices for generating these models 

Who Should Attend

IC design engineers, EM/IR engineers, Power Integrity engineers, CAD/methodology engineers

Speaker

  • Devansh Saxena
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