Electro-Thermal Signoff For Next Gen 3DICs
Multi-die designs, 2.5D and 3D, have been rising in popularity as they offer tremendously increased levels of integration, a smaller footprint, performance gains and more. While they are attractive for many applications, they also create design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterparts, we must account for electrical and thermal coupling between dies as well.
Traditionally, thermal, power and signal integrity analysis of each SoC is done independently with margins or guard-bands based on historical/empirical experience. As we move to 3DICs, this approach can lead to over/under design or silicon failures, and it becomes increasingly important to use comprehensive multi-die workflows with foundry-certified accuracy for such multiphysics simulations; this can be further extended to include mechanical stability issues like PCB warpage and electromagnetic coupling between adjacent high speed signal tracks.
This webinar will spotlight a detailed analysis of Ansys’ signoff solution for next-generation 3DIC systems, including:
- Power integrity signoff of multi-die systems using the big data platform of Ansys RedHawk-SC
- Chip-package-system co-analysis including thermal and mechanical effects
- Uncovering various failure mechanisms and gaining signoff confidence for first-time silicon success.