Ansys medini analyze supports key safety analysis methods at various levels of a chip, ranging from IP Design of integrated components, up to SoCs and electronic boards.
Ansys medini analyze supports best-practice workflows that graphically link specific areas of the semiconductor design to key functions within the electronics architecture. This allows engineers to analyze and address potential failure modes as they verify the functional safety of semiconductor components. Engineers can efficiently and consistently execute the safety-related activities such as the FMEDA, required by safety standards like ISO 26262: 2018 part 11.
Streamline and automate functional safety analysis across the entire electronics architecture — including down to the chip level. Any inconsistencies in the functional safety analysis are eliminated, and confirmation reviews and assessments are accelerated.
ZF Group Harmonizes and Accelerates Functional Safety Analysis with Ansys medini analyze.
According to Günter Gäbelein, Safety Assessor at ZF Friedrichshafen AG, “As a systems supplier for passenger cars, commercial vehicles, and industrial technology, ZF Friedrichshafen AG places great emphasis on agility and innovation. To support exciting developments like autonomous driving and electric mobility, our R&D process must be fast, cost effective, and technically precise. More and more projects are taking advantage of synergies provided by medini analyze. In a medium-size project, more than 300 hours of effort can be saved by the one-tool solution and the interfaces to third-party tools for architectures. ZF is a strong advocate for model-based engineering, and medini analyze helps to reduce the complexity of analysis for embedded systems."
CAPABILITIES
With Ansys medini analyze for semiconductor safety, seamlessly exchange IP design between hardware designers and safety analysts. Engineers can perform derivation of base failure rates for a hardware design, automatic determination of failure distributions based on design data (e.g., die area, gate counts), as well as FMEA, FMEDA and FTA analysis based on the hardware design. Teams can reuse and adapt FMEDA data from previous designs and export configurable FMEDA result data for the handover of safety data to integrators.
By reducing development costs and time to market — while maximizing innovation and product confidence — Ansys medini analyze can help companies achieve a significant competitive advantage
Implement qualitative methods (e.g., FMEA, quantitative analysis, failure rate prediction, FMEDA and diagnostic coverage analysis, or FTA), as well as dependent failure analysis. These methods are integrated and carried out at various levels over a consistent set of design models.
ISO 26262 Semiconductor Workflow Ansys medini analyze facilitates ISO 26262 compliance and remains a trusted solution for streamlining and automating functional safety analysis across the entire electronics architecture, down to the chip level.
Predict failure rates of your chips using built-in handbooks such as IEC 61709, IEC 62380, SN29500, and many more. Distribute failure rates along die area or element/gate/cell counts of an imported IP design, both for permanent and transient failures. Define stress parameters such as temperature and analyze the impact for FMEDA and PMHF to meet safety and reliability targets.
Collaborate as a safety engineering team by sharing, comparing and merging safety projects. Integrate with task management systems for workflow support. Export your safety analysis (e.g. FMEDA) in a configurable way to field teams and customers for adaptation to the target system context
Capture and trace your safety requirements together with your chip design. Import, export and round-trip from/to requirements management for systems (e.g., IBM® Rational® DOORS®, PTC Integrity™, Jama Software) and design tools such as Cadence Incisive Simulator or Synopsys IC Compiler. Validate the standard compliance of your safety mechanisms with fault injection by third-party verification tools.
RESOURCES & EVENTS
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