SiFive Maximizes Compute Density With RISC-V Cores
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across various markets and applications.
In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and mW (e.g., SPECint2006/mm2) has been a driving goal for SiFive’s portfolio of RISC-V processor cores.
One of the keys to delivering high performance in a tight area is carefully managing dynamic power at all stages, from early RTL analysis and optimization using realistic activity to pushing the limits on efficient power distribution networks that satisfy all voltage drop requirements. SiFive and Ansys will describe design flows to meet these objectives.
Develop design flows that meet these objectives:
- Achieve maximum compute density, focusing on compute horsepower per mm2 and mW (e.g., SPECint2006/mm2).
- RISC-V processor cores are designed with the goal of high performance in a compact area
- Effective dynamic power management at all stages is crucial for delivering high-performance
- Careful RTL analysis and optimization using realistic activity for power management
- Efficient power distribution networks that meet all voltage drop requirements are vital in achieving performance goals