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Reducing Semiconductor Packaging Defects with Ansys Tools

Ansys Semiconductor Manufacturing Webinar Series: Part 2 of 3.

Join us on Thursday, May 23rd for an in-depth discussion on reducing defects in the semiconductor packaging process.

Learn more about the webinar series!


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Semiconductor packaging involves integrating heterogeneous chips with different functionalities into a single IC that is assembled onto a PCB with other components inside an electronic device. With more functionalities packed into a System-on-IC (SoIC) through 3DIC packaging technologies, packaging processes are incredibly complex today. This talk will demonstrate using Ansys tools to model packaging assembly processes to reduce manufacturing defects in such heterogeneous ICs. In addition, this talk will address the selection and handling of sustainable materials for packaging processes.

What you will learn

  • Reduce manufacturing defects during packaging
  • Modeling packaging assembly
  • Selection and handling of material for sustainability

Who should attend

Engineers and Engineering Managers/Directors, packaging, board or chip R&D teams, operations teams working with manufacturing vendors, design for manufacturing teams, tech development and reliability teams


  • Arkaprabha Sengupta, Lead Application Engineer, Ansys
Icepak Thermal