Safe & Secure Systems
Dramatically decrease analysis efforts with efficient application of quality, safety, reliability and cybersecurity analysis methods at the system, item, software, hardware and PCB levels.
Dramatically decrease analysis efforts with efficient application of quality, safety, reliability and cybersecurity analysis methods at the system, item, software, hardware and PCB levels.
High Level Features
Ansys safety & cybersecurity threat analysis software facilitates model-based safety analysis, safety concept creation, safety management and cybersecurity assessment for safety-critical electrical and electronic (E/E) and software (SW) controlled systems.
Using this software, engineers can deliver safe and secure products, reduce time to market, maximize profit margins and comply with standards like ISO 26262, IEC 61508, ARP 4754A/ARP 4761, ISO 21448 and ISO 21434.
Release Date: January 2022 R1
In Ansys 2022 R1, Ansys medini analyze delivers new features that further enable the efficient holistic application of safety, reliability, and cybersecurity analysis methods, enabling the user to comply with the latest applicable industry domain standards.
Extended DSM Safety Cockpit with KPI support & project status. The safety cockpit provides an easy to use, configurable dashboard to get an overview on multiple safety plans and their status.
Fault Tree Analysis fully compliant with ARP4761: The quantitative FTA evaluation now supports the industry best-practice for calculating Q/T considering event dormancies. Convenient utilization of planning data in FMEA: medini analyze and the Digital Safety Manager are fully integrated.
ISO 21434 Damage Scenarios: the automotive cybersecurity standard, ISO 21434, the concept of Damage Scenario is introduced. Damage Scenarios are used to model top-level effects caused by potential cybersecurity attacks. Impact ratings for risk determination are based on Damage Scenarios.
By acting as a central hub for gathering data, managing resources, planning and automating many process steps, Ansys enables a comprehensive view on safety.
The Ansys Safety Analysis software suite streamlines safety and security analysis, decreasing efforts and costs.
During system design, safety analyses (HAZOP, HARA, FHA, FTA, FME(C)A, FMEDA, etc.) are applied to verify that the design is safe. This enables full traceability, consistency and automation of previously time-consuming and error-prone manual tasks. Necessary documentation of the safety case is generated by the tool.
Ansys medini analyze enables the systematic identification of SOTIF risks in the hazard and risk analysis stage, as well as the consideration of design limitations and triggering conditions. Once these are identified, countermeasures can be planned to meet safety requirements. These measures and requirements are traced in Ansys medini analyze to the functional or architectural updates that are completed during the implementation of the system. Ansys medini analyze provides analysis methods like cause-effect-nets, System Weakness Analysis tables, and event trees, which make systematic analysis, understanding and elimination of SOTIF hazards possible.
This enables diverse teams — working to meet functional safety and SOTIF standards across system, electronics, embedded software, and other areas — to collaborate easily and more seamlessly.
This model-based, integrated tool provides end-to-end traceability, along with powerful collaboration, task management and reporting capabilities.
Ansys medini analyzes capabilities for semiconductors facilitate the process of mapping blocks of the semiconductor design to system components. Furthermore, it determines failure rates for the overall chip design and distributes it according to criteria, as die area occupation or gate count to the functional blocks. In a subsequent step, a Failure Mode, Effects and Diagnostics Analysis (FMEDA) can be done to evaluate the overall design with respect to the coverage rates of failure modes by safety mechanisms. In this manner, engineers can quickly identify any design weaknesses in semiconductors, whether caused by design errors or environmental conditions, and address them to mitigate the impact on day-to-day safe performance.