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17 Equations that changed the World

Mathematics has been a constant part of our lives forever and is used in many ways in our everyday lives. Created by Ian Stewart, listed on Dr. Paul Coxon’s Twitter account, and discussed on mathematics blogger Larry Philip’s site is a list of the “17 Equations that Changed the World,” many of which have been mentioned on the Big Bang Theory TV series.

However, the list is incomplete. There are numerous equations that help to determine the reliability of electronics products that Ansys believes should be included. These formulas are all integral to the Ansys Sherlock software and are the basis for the validation of the results obtained in an ADA analysis. Let’s take a look at them.


Plated through holes (PTHs), also known as plated through vias (PTVs), are holes drilled through multilayer printed circuit boards (PCBs) that are electrochemically plated with a conductive metal (typically copper). These plated holes provide electrical connections between layers.

Because these plated holes are metallurgically bonded to annular rings on the top and bottom of the PCB, they act like rivets and constrain the PCB. This constraint subjects the PTH to stresses when the PCB experiences changes in temperature.

PTH fatigue is the circumferential cracking of PTHs due to the differential expansion between the copper plating (~17 ppm) and the out-of-plane coefficient of thermal expansion (CTE) of the printed board (~45 to 70 ppm) during temperature variations. This failure mechanism was first reported by Bell Laboratories in 1976.

What are the drivers for PTH fatigue?

PTH fatigue is influenced by maximum temperature, minimum temperature, PTH diameter, PTH copper plating thickness, copper plating material properties (ductility, yield strength), printed board thickness, printed board out-of plane material properties (CTE, elastic modulus), and defects within the copper plating (voids, folds, etch pits, etc.).

How does the software assess PTH fatigue?

The software calculates a time to failure using the industry-accepted model published in IPC-TR-579, "Round Robin Reliability Evaluation of Small Diameter Plated Through Holes in Printed Wiring Boards". Life calculation for PTHs subjected to thermal cycling is a three- step process. The first step is to calculate the stress being experienced by the copper barrel of the PTH. This is provided by the equations below, where α is coefficient of thermal expansion (CTE), T is temperature, E is elastic modules, h is the board thickness, d is the hole diameter, t is the plating thickness, and E and Cu correspond to board and copper properties, respectively.

Once the stress is determined, the strain range is calculated by the following, where Sy is the yield strength of copper:

This strain is adjusted by two constants: a strain distribution (Kd) factor and a quality factor (KQ).

While the strain distribution factor tends to be set to a value of 1.6, KQ is dependent upon the quality of the PTH (i.e., the presence of defects such as voids, cracks, folds, etc.). The quality factor can range from 0 to 10 with the following delineations:

  • Extraordinary (KQ = 10)
  • Superior (KQ = 8.7)
  • Good (KQ = 6.7)
  • Marginal (KQ = 4.8)
  • Poor (KQ = 3.5)

Once the strain range is defined, the cycles to failure (Nf) can be calculated iteratively, with Su being the ultimate tensile strength and Df being ductility of the plated copper.

Reviewing the equations above, it can be seen that the designer and PCB manufacturer have the following controls over the reliability of PTHs:

  • Out-of-plane CTE of the printed board
  • Plating thickness
  • Aspect ratio (hole diameter over board thickness)
  • Plating material properties (i.e. strength and ductility) and plating quality


Solder joints, also known as interconnects, provide electrical, thermal, and mechanical connections between electronic components (passive, discrete, and integrated) and the substrate or board to which it is attached. Solder joints can be a first-level (die to substrate) or second-level (component package to printed board) connection. This module assesses the thermo-mechanical fatigue behavior of second- level solder joints.

During changes in temperature, the component and printed board will expand or contract by dissimilar amounts due to differences in the CTE. This difference in expansion or contraction will place the second- level solder joint under a shear load. This load, or stress, is typically far below the strength of the solder joint. However, repeated exposure to temperature changes, such as power on/off or diurnal cycles, can introduce damage into the bulk solder. With each additional temperature cycle, this damage accumulates, leading to crack propagation and eventual failure of the solder joint.

The failure of solder joints due to thermo-mechanical fatigue is one of the primary wearout mechanisms in electronic products, primarily because inappropriate design, material selection, and use environments can result in relatively short times to failure.

What are the drivers for thermo-mechanical solder joint fatigue?

Thermo-mechanical solder joint fatigue is influenced by maximum temperature, minimum temperature, dwell time at maximum temperature, component design (size, number of I/O, etc.), component material properties (CTE, elastic modulus, etc.), solder joint geometry (size and shape), solder joint material (SnPb, SAC305, etc.), printed board thickness, and printed board in-plane material properties (CTE, elastic modulus).

How does the software assess thermo-mechanical solder fatigue?

The software calculates time to failure using strain energy. The detailed methodology is provided by the equations below. The first equation describes the force exerted on a solder joint during a thermal cycle:

In this equation, α is the CTE, T is temperature, L is one half component length, F is force, E is elastic modulus, A is the effective solder joint area, G is the shear modulus, h is thickness, and ν is the Poisson ratio. The strain range induced in the solder joint during the thermal cycle is.

The equations above are package-specific and account for the geometry, interconnect structure, and material properties of the component and PCB. The stress on the solder joint is determined using the computed forces, and this stress is combined with the strain to determine the energy dissipated by the solder during a thermal cycle through the equation (see right).

The resulting strain energy is used to compute the number of cycles to failure for the component under temperature cycling using equations developed by Syed (see right).


The Shock/Vibration module in Sherlock utilizes the finite element method to predict the circuit card assembly (CCA) response during mechanical shock and harmonic or random vibration events. The board response results are then used to make predictions on the robustness of the CCA to these events. In the case of vibration, high cycle fatigue predictions are made to determine the life of the interconnect (lead and solder joint). The shock analysis results are used to determine if a critical stress due to board bending is exceeded.

Second-level interconnects provide electrical, thermal, and mechanical connections between electronic components (passive, discrete, and integrated) and the substrate or board to which it is attached. The vibration portion of the module assesses the high cycle fatigue behavior of second-level interconnects.

How does the software assess vibration?

During exposure to vibration, the CCA responds by cyclic deflecting in a manner that corresponds to its natural frequencies. These natural frequencies are dependent on the geometry, stiffness, mass, and boundary conditions of the CCA. The software automatically generates the model and then utilizes the open-source finite element analysis (FEA) engine CalculiX to conduct the shock and vibration response shows the vibration analysis of a circuit board using

CalculiX. The CalculiX FEA analysis engine was originally developed by Guido Dhondt and is open source covered under GNU General Public License. The naming conventions and input style formats for CalculiX are based on those used by ABAQUS, a proprietary, general- purpose finite element code developed and supported by Hibbitt, Karlsson & Sorensen, Inc. (HKS). A discussion on CalculiX can be found at STRUCTURE, for validation of the CalculiX solver, please visit bConverged (

The software generates a three-layer shell model of the circuit card assembly with six-node triangular elements that define the top components, bottom components, and printed wiring board. These six-node shell elements are expanded into 15-node three-dimensional wedge elements automatically by CalculiX during analysis.

The output of the FEA is post-processed by the software, and the maximum board level strains for every component are recorded for use in determining whether that component fails during exposure to the shock and vibration loads. There are four types of vibration analyses that the software conducts:

  1. Natural frequency extraction
  2. Single-point harmonic vibration
  3. Swept harmonic vibration
  4. Random vibration

The first analysis, natural frequency extraction, is used to extract the fundamental frequencies of the circuit card assembly.

For a reference describing the theory behind CalculiX CrunchiX the user is referred to:

Dhondt, G. The Finite Element Method for Three-Dimensional Thermomechanical Applications, Wiley, 2004


The failure of solder joints due to vibration is based upon a technique similar to the one developed by Steinberg. The main modification is converting from a displacement-based criteria to a board-level strain criteria. The Steinberg critical PCB deflection, at which a component will survive 10 million cycles during harmonic vibration or 20 million cycles during random vibration, is:


B is length of PCB parallel to component

c is a component packaging constant (typically between 0.75 and 2.25) h is the PCB thickness

r is a relative position factor and is 1.0 when component is located at the center of the PCB L is component length

The main issue with this approach is that it is limited to simple board geometries (since the maximum deflection is always assumed to be at the center of the PCB) and doesn’t account for board curvature. By utilizing finite element modeling, the software eliminates some of the variables in the equation since they are accounted for in the FEA model. These include board length (B), position factor (r), and board thickness (h), and the equation is simplified to:

ζ is analogous to 0.00022B (B is the edge length of the PCB ) but represents strain

c is a component packaging constant (typically between 0.75 and 2.25)

L is component length

The software uses this critical strain value and the FEA-computed strain values to make fatigue predictions using the Basquin equation


NFEA is the predicted number of cycles to failure

Nc is 10E6 for harmonic of 20E6 for random vibration

εc is the critical strain value and is a function of component type and size

εFEA is maximum printed circuit board strain recorded at the component

b is the fatigue exponent and is dependent on the solder alloy


Currently, the software does not make fatigue predictions based on a mechanical shock loading. Mechanical shock is instead viewed as an overstress event and is based on exceeding a predefined board level strain. This analysis is an extension to the type of information provided in IPC-9704 for ball grid array (BGA) devices. The software utilizes these limits as the generic values for all components.

If the strain level anywhere at the parts locations exceeds the acceptable amount, the part is considered to fail the shock robustness portion of the analysis. Figure 3 shows plot of Maximum allowable principal strain vs. strain rate for circuit boards with variable thickness. The shock analysis utilizes the CalculiX-based FEA to determine the circuit card assembly’s response and the part-level strains that occur during the shock event.


Almost all materials exhibit a change in physical dimensions when subjected to temperature changes. The degree of expansion in response to a change in temperature is called the coefficient of thermal expansion (CTE).

CTE is critical because when two materials with different CTE are joined, a stress is imparted because of the resultant displacement mismatch. This is the main driver of thermal- mechanical fatigue of electronic components.

During changes in temperature, the component and printed board will expand or contract by dissimilar amounts due to differences in the CTE.

This difference in expansion or contraction will place the second-level solder joint under a shear load. This load, or stress, is typically far below the strength of the solder joint. However, repeated exposure to temperature changes, such as power on/off or diurnal cycles, can introduce damage into the bulk solder.

The calculation of the CTE of the PCB is critical as input for determining thermo-mechanical fatigue of solder interconnects.

How is the PCB CTE calculated?

The Sherlock software uses lamina theory for calculating the CTE of PCB. PCBs are composed of alternating layers of glass-reinforced epoxy laminate/prepreg and copper foil.

The mechanical properties of the laminate and copper foil are:

  • Coefficient of thermal expansion, in plane (CTExy)
  • Coefficient of thermal expansion, out of plane (CTEz)
  • Elastic modulus, in plane (Exy)
  • Elastic modulus, out of plane (Ez)

The stackup tool allows the copper thicknesses to be in ounces/milliliters/microns, where 1 oz = 35 microns = 1.4 mil.

Term definitions

  • CTExypcb is the coefficient of thermal expansion, in-plane of the PCB
  • CTEzpcb is the coefficient of thermal expansion, out of plane of the PCB
  • Exypcb is the elastic modulus, in plane of the PCB
  • Ezpcb is the elastic modulus, out of plane of the PCB
  • CTExyln is the coefficient of thermal expansion, in-plane of layer n (the first and last layer will always be copper)
  • CTEzln is the coefficient of thermal expansion, out of plane of layer n
  • Exyln is the elastic modulus, in-plane of layer n
  • Ezln is the elastic modulus, out of plane of layer n
  • tln is the thickness of layer n
  • tpcb is the overall thickness of the PCB

The copper layers are computed assuming a combination of copper and unreinforced resin rich regions. This is a critical aspect of the CTE calculation, especially when the copper weight increases above 2 oz.

This is just the beginning of the validation formulas that are integral to Sherlock. In a future white paper, Ansys will address flex cracking of components, cyclic bending, conductive anodic filament (CAF), and interconnect (IC) wearout.

So, as previously stated, there are numerous equations that provide reliability validation. Look for the second white paper to illustrate the rest that are currently in Ansys Sherlock and provide the basis for a physics of failure (PoF) approach to reliability assessments.

Don’t hesitate to contact Ansys with any questions.


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