Skip to Main Content

 

Webinar

Voltage-Timing Signoff for Next Generation Ultra Low Voltage Designs

Today's advanced 16/7/5nm/3nm SoCs are faced with increased variation effects as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law the threshold voltages fail to continue to scale. Traditionally dynamic voltage drop (DvD) signoff and timing signoff are done independently with margins/guard-banding based on historical/empirical experience. As we move to advanced SoCs this approach can lead to chip failures. Ansys provides comprehensive workflows with foundry-certified accuracy for multiphysics simulations across power integrity and its impact on timing critical paths.

Join us for this webinar for a detailed analysis of Ansys’ multiphysics reliability signoff solution for next-generation ultra-low voltage SoCs.

  • Learn how Ansys SeaScape and Ansys FX technologies combine to build a comprehensive voltage-timing solution that meets industry needs.
  • Discover how this Ansys workflow can accurately model dynamic voltage drop impact on timing and enable chip designers to quickly identify the important set of violations that they need to fix prior to signoff.

SHARE THIS WEBINAR

现在就开始行动吧!

如果您面临工程方面的挑战,我们的团队将随时为您提供帮助。我们拥有丰富的经验并秉持创新承诺,期待与您联系。让我们携手合作,将您的工程挑战转化为价值增长和成功的机遇。欢迎立即联系我们进行交流。