Production proven path-based timing and clock-tree analysis

ANSYS Path FX complements existing sign-off and physical design flows. It has the performance to evaluate all of the timing paths and clock trees in a SoC for delay and variance for even the largest designs. ANSYS Path FX has production-proven accuracy to tackle the most advanced manufacturing processes, the functionality to account for all critical contributors to delay and constraints across multiple process, voltage, temperature corners and scenarios.

ANSYS Path FX makes it practical to calculate timing with variation on a full SoC without taking any shortcuts. With a fully threaded and distributed architecture and the ability to run on thousands of CPUs, turnaround time scales inversely with the number of CPUs available.

ANSYS Path FX delivers:

Complete Path-based Critical Path Timing
ANSYS Path FX can simulate thousands of paths using standard cell models or transistor-level SPICE models, providing both corner and statistical timing results.

Full Clock Tree Analysis
ANSYS Path FX automatically identifies and simulates every clock path in your design.

Ultra-low Voltage Transistor-level Simulation
ANSYS Path FX leverages the SPICE transistor models and full waveform propagation to provide the accuracy needed to get reliable results at ultra-low voltage and advanced processes. Miller-capacitance and other effects are handled correctly, with no shortcuts.

Delay, Constraints and Variation
ANSYS Path FX simulates delays, slews and constraints. The simulator is fully statistical and handles non-gaussian behavior at low voltage and advanced process nodes.

Reduced Turnaround Time
ANSYS Path FX is threaded and distributed, dramatically reducing turnaround time and memory requirements.

Easy Integration
ANSYS Path FX reads industry standard files and generates a rich set of reports and SDF for back-annotating results into your flow.