ANSYS Totem is a transistor-level power noise and reliability simulation platform for analog, mixed-signal and custom digital designs. Totem’s core technologies include foundry-certified extraction and simulation engines embedded within a powerful GUI environment that enable layout-based result analysis and design fixing. The software can analyze large full-chip designs, including package and substrate parasitics with SPICE-level accuracy. It helps designers meet increasingly stringent power and reliability requirements for IPs and/or analog and custom designs.
Watch this video to learn how Totem addresses power noise and reliability analysis for full-custom, analog, and mixed-signal designs.
Totem is used to validate and sign-off custom macros or IPs (analog, custom digital, memory) against static and dynamic voltage drop. It is also useful for power and signal electromigration (EM) requirements. Multiple foundries have certified ANSYS Totem for EM and electrostatic discharge (ESD) rules for advanced technology nodes (20/16/14 nm).
Totem also creates detailed models of the IPs, verifying that these are connected appropriately at the SoC level and that operation at the full-chip level is not adversely affected due to poor design or noise coupling issues. Totem’s model-generation capabilities enable seamless IP integration at the SoC level for full-chip mixed-signal verification.
Totem has been successfully correlated with silicon measurements for multiple technology nodes. It can be used from early in the design phase, during prototyping through sign-off.