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ANSYS RedHawk 2014

The latest release of industry-standard power noise and reliability sign-off platform is FinFET ready, delivering performance, capacity and coverage for the next generation of low-power, high-performance designs.

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ANSYS REDHAWK-CPA

IC package impacts the integrity and reliability of on-chip power. RedHawk-CPA enables chip-package co-analysis for package-aware sign-off for next generation low-power, high-performance designs.

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ANSYS RedHawk

ANSYS RedHawk is an industry-standard sign-off platform for system-aware SoC power, noise and reliability. The power integrity platform enables power noise closure and sign-off for low-power, high-performance SoCs using sub-20 nm FinFET and other advanced technologies.


arrow Watch this video to learn how RedHawk is ready for 16nm FinFET based designs.

RedHawk’s advanced engines and simulation capabilities deliver significantly high capacity and improved turn-around times (TATs) for full-chip IR/dynamic voltage drop, power/signal electromigration (EM) and electrostatic discharge (ESD) analyses. It enables RTL-to-GDS power closure, SoC-level IP verification and chip-aware system analyses.

image of    Comprehensive power noise and reliability sign-off platform

Comprehensive power noise and reliability sign-off platform

RedHawk’s extraction, simulation and EM/ESD engines have been certified by multiple foundries and silicon-validated on sub-20 nm designs. Our software has enabled thousands of successful tape-outs; the technology is used by more than 90 percent of the top 20 semiconductor, top 10 mobile and top 10 mobile IC companies in the world.

Using RedHawk, chip and system design engineers can meet the increasing constraints of power−performance−price targets for their designs.