ANSYS PathFinder is an electrostatic discharge (ESD) planning, verification and sign-off solution for full-chip SoC and IP designs. It is applied in layout and circuit-level analysis to identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events. A number of foundries have certified the technology for its ability to perform accurate interconnect parasitic extraction, ESD simulation and electromigration (EM) or current-density rule handling.
Source: An Automated Approach for Verification of On-Chip Interconnect Resistance for Electrostatic Discharge Paths. EOS/ESD symposium 2011, H. Gossner et. al, Infineon Technologies/Intel Mobile Communication.
Source: EOS/ESD Current Density Analysis Methodology for Robust I/O ESD Network Design. 2013 International ESD Workshop, Chanhee Jeon, et.al, Samsung Semiconductor.
PathFinder includes comprehensive layout connectivity and interconnect failure analysis capabilities. It provides extensive design prototyping features for early ESD planning, especially for large, multi-voltage island SoCs using advanced sub-20 nm process technology nodes.
PathFinder replaces traditional visual plot checks or DRC-based checks, providing an accurate and predictable ESD sign-off methodology. It analyzes the layout, ESD protection cell placement and ESD current flow through interconnects. For IP level verification, the technology performs entire power/ground/substrate network extraction and detailed circuit simulation to identify stressed device junctions during an ESD event. At the full-chip or SoC level, PathFinder performs an extensive suite of checks. For example, it can verify efficiency and robustness of an ESD discharge path by performing detailed extraction and connectivity simulations. Or it can perform detailed and accurate current density simulations to root-cause weaknesses in the ESD buses or imbalances in clamp/diode hook-up.