Ansys PathFinder-SC Datasheet
Ansys PathFinder-SC™ is the next-generation SoC power noise signoff platform designed to enable sub-16nm design success. PathFinder-SC provides a high-capacity solution for verifying the protective circuitry found on all chips that protect them from electrostatic discharge (ESD) and damage from voltage spikes. This technology has become increasingly pivotal as silicon technology continues to shrink to 3nm and below, where these tiny transistors need to be protected by critical ESD circuitry that is checked, verified, and signed off with PathFinder-SC. PathFinder-SC is built on Ansys SeaScape™, the world’s first custom-designed big data platform for electronic system design and simulation. SeaScape provides per-core scalability, flexible design data access, instantaneous design bring-up, MapReduce-enabled analytics and many other revolutionary capabilities. SeaScape technology allows PathFinder-SC to deliver over 5x faster turnaround for ultra-large SoCs, which makes it ideal for today’s large, high-speed semiconductor designs in artificial intelligence, imaging, networking, and 5G and 6G telecommunications.