DAC 2016

Reinventing Power Noise Sign-off

Elastic Compute Platforms for Chip-Package-System Innovation
 
The design-process interactions in today’s chips pose significant challenges to designers. A chip has to work in the context of the system it goes into, which involves moving beyond functional integrity into power, noise and reliability issues. As a designer, you typically face one or more of the following design challenges. How do you:

  • Ensure that the design meets the required power-performance targets?
  • Make sure that electromigration reliability is validated against true thermal conditions?
  • Ensure protection against potential ESD events?
  • Consider the impact of package on a chip’s power delivery network?
  • Make sure your design is EMI-compliant at the system level?

Visit us at DAC Booth 1449 to hear our domain experts and industry-leading customers share their best practices for creating the most advanced, high-performance, low power designs for automotive, mobile, IoT and other applications.

Visit us also at another place - ARM Connected Community  -  Booth 1748,   Samsung Booth 607,   TSMC Booth 1933

Industry presentations

Automotive Simulation to Ensure Safety and Reliability

Monday 4:15 PM; Tuesday 12:05 PM

Automotive Simulation to Ensure Safety and Reliability

Shrinking IoT Product Development Time from Concept to Production with Simulation

Monday 12:05 PM; Tuesday 4:15 PM

Shrinking IoT Product Development Time from Concept to Production with Simulation

Simulation Platforms for Mobile System Design

Tuesday 4:15 PM; Wednesday 12:05 PM

Simulation Platforms for Mobile System Design

 
 

Foundry presentations

Global Foundries
Intel Custom Foundry
samsung
tsmc

 

 

Best Practices Presentations



  • Ensuring First Time Silicon Success for Ultra-Large Sub-16nm SoC Designs

    Ensuring First Time Silicon Success for Ultra-Large Sub-16nm SoC Designs

  • Power and Reliability Analysis of Next Generation 3DIC and Fan-out Wafer-level Packaging

    Power and Reliability of Next Generation 3DIC and Fan-Out Wafer-level packaging

  • A Step-by-step Approach to Ensure ESD Robustness for IP and SOCs Using ANSYS PathFinder

    A Step-by-Step Approach to Ensure ESD Robustness for IP and SOCs Using ANSYS Pathfinder

  • Reference Flows with Accurate On-die Modeling for System Level PI, SI, Thermal and ESD

    Reference Flows with Accurate On-die Modeling for System Level PI, SI, Thermal and ESD

  • Optimizing Die-size Through Safe Reduction of PDN Over-design Using In-design ECO Fixes and Provable Analysis Coverage

    Optimizing Die-size Through Safe Reduction of PDN Over design Using In-design ECO Fixes and Provable Analysis Coverage

  • Prevent Power Noise and Reliability Failures in Next-generation IPs and Analog and Mixed Signal Designs

    Prevent Power Noise and Reliability Failures in Next- generation IPs and Analog and Mixed Signal Designs

  • Six Steps to Low Power RTL Design

    Six Steps to Low Power RTL Design

  • Monday, 4 PM
    Wednesday, 11 AM

  • Monday, 1 PM
    Tuesday, 5 PM
    Wednesday, 3 PM

  • Wednesday, 12 PM

  • Monday, 5 PM
    Wednesday, 1 PM

  • Tuesday, 1 PM
    Wednesday, 10 AM

  • Monday, 12 PM
    Tuesday,4 PM

  • Tuesday, 12 PM
    Wednesday, 2 PM

Register

 

User-driven Workshops


Workshop 1 - Industry Trends on Low Power RTL Design and Analysis

Industry Trends on Low Power
RTL Design and Analysis

Monday, 10:00 AM - 12:00 PM

Workshop 2 - In-design Optimization for Accelerated Design Closure

In-design Optimization for Accelerated Design Closure

Monday, 2:00 PM - 4:00 PM

Workshop 3 - Chip-Package-SystemSimulation for Power, Signal and Thermal Analysis

Chip-Package-System Simulation
for Power, Signal and Thermal

Tuesday, 10:00 AM - 12:00 PM

Workshop 4 - Reliability Challenges for Advanced SoC and IP Designs

Reliability Challenges for
Advanced SoC and IP Designs

Tuesday, 2:00 PM - 4:00 PM

Please contact your account manager to register

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