Reinventing Power Noise Sign-off
Elastic Compute Platforms for Chip-Package-System Innovation
The design-process interactions in today’s chips pose significant challenges to designers. A chip has to work in the context of the system it goes into, which involves moving beyond functional integrity into power, noise and reliability issues. As a designer, you typically face one or more of the following design challenges. How do you:
- Ensure that the design meets the required power-performance targets?
- Make sure that electromigration reliability is validated against true thermal conditions?
- Ensure protection against potential ESD events?
- Consider the impact of package on a chip’s power delivery network?
- Make sure your design is EMI-compliant at the system level?
Visit us at DAC Booth 1449 to hear our domain experts and industry-leading customers share their best practices for creating the most advanced, high-performance, low power designs for automotive, mobile, IoT and other applications.
Best Practices Presentations
Ensuring First Time Silicon Success for Ultra-Large Sub-16nm SoC Designs
Power and Reliability of Next Generation 3DIC and Fan-Out Wafer-level packaging
A Step-by-Step Approach to Ensure ESD Robustness for IP and SOCs Using ANSYS Pathfinder
Reference Flows with Accurate On-die Modeling for System Level PI, SI, Thermal and ESD
Optimizing Die-size Through Safe Reduction of PDN Over design Using In-design ECO Fixes and Provable Analysis Coverage
Prevent Power Noise and Reliability Failures in Next- generation IPs and Analog and Mixed Signal Designs
Six Steps to Low Power RTL Design
Monday, 4 PM
Wednesday, 11 AM
Monday, 1 PM
Tuesday, 5 PM
Wednesday, 3 PM
Wednesday, 12 PM
Monday, 5 PM
Wednesday, 1 PM
Tuesday, 1 PM
Wednesday, 10 AM
Monday, 12 PM
- Tuesday, 12 PM
Wednesday, 2 PM