ANSYS Totem Capabilities
Silicon-Proven Analog and Mixed-Signal EM/IR Sign-off
Totem’s static analysis helps you verify the robustness of your IP and full-chip design’s power grid. Its dynamic voltage drop analysis exposes design weakness caused by simultaneously switching transistors, and reflects the actual operation of a circuit, including the time-varying current drawn and its interplay with capacitive and inductive parasitics of the power delivery network, which can cause power droop or ground bounce.
Totem analyzes noise propagation through the entire power delivery network, from the system/PCB to the on-chip power grid and substrate network. Validation of Totem’s simulation results against silicon by various customers speaks to its accuracy. Silicon correlation spans IPs to custom circuits and mature to advanced technology nodes, including 7nm.
As a further endorsement of its accuracy, Totem, the industry’s only sign-off solution for analog and mixed-signal power noise integrity and reliability, is used by all major semiconductor companies in their production flow.
Analysis of Power Management ICs
The explosive growth of mobile and IoT devices, and the energy efficiency capabilities that are required of them, are driving the need for power management IPs. Any design weakness that leads to increased local current density, voltage drop or noise coupling impacts the power delivery. It is important to identify such weaknesses, which are more specific to power management IC’s. Because power management IPs get integrated into a wide range of full-chip applications, the weaknesses also have to be identified in the context of a full-chip design, which is even more challenging.
Totem, as a comprehensive simulation platform for voltage drop, reliability (EM/ESD) and noise coupling analyses of full-chip analog, mixed-signal I/O designs, can identify design weaknesses using specific checks that are ideal for power management: resistance, current density and guard ring analysis. This verification is done not only during the design phase of a PMIC module or IP, but also during its integration at the full-chip level.
Analysis of High-Speed Gigabit SerDes IP
Due to the nature of high-speed SerDes, the common challenges that designers face are jitter, which affects error rate; power, which impacts energy per bit; and reliability, which affects the long-term operation of the IC. Use of advanced process technologies adds obstacles by bringing in higher current densities, which have a great impact on power integrity and EM reliability due to thermal issues. To mitigate the risk of failure, it is critical to identify power noise and reliability issues with SerDes IPs, from individual building blocks to full IPs.
Totem delivers a comprehensive simulation framework for voltage drop, substrate noise, reliability (EM/ESD) and noise coupling analyses of analog, mixed-signal I/O designs. In addition, it generates power models of a SerDes IP for integration into an SoC for full-chip IR drop, electromigration and ESD integrity. These models increase the reliability of the SerDes at the full-chip level.
Substrate Noise Analysis
The most common source of substrate noise in a circuit is due to the noise coupling from high-speed digital circuitry to sensitive analog and RF blocks. This calls for a true mixed-signal power noise and reliability analysis.
Totem is the industry’s only mixed-signal EM/IR tool with a track record of foundry sign-off for substrate noise analysis. It helps you assess the noise impact on timing, frequency domain analysis and the quality of the guard ring, leading to faster sign-off closure.
NXP leveraged this capability to integrate multiple radios onto a single chip while minimizing substrate noise from the high-speed digital signals on-chip. Their analysis results correlated well with silicon.
Debug and Root Cause Analysis
Root cause analysis and what-if fixing are critical capabilities for any analysis tool, especially for a power noise integrity and reliability solution dealing with reducing noise margins, increasing thermal effects and minimizing package and PCB parasitics. On mixed-signal chips containing digital, analog and RF, the complications are even more pronounced.
Totem’s layout-based analysis and built-in graphical interface offers full visibility into the cause of failures by overlaying simulation results on top of the layout. This gives you quick interactive root-cause analysis and what-if fixing, which significantly reduces the debug cycle.
Totem’s versatile, multifunctional GUI gives the look and feel of a layout editor while providing full visibility into simulation results through sophisticated multitab, multipane capabilities.
IP Sign-off and SoC Integration
IPs are integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the predictions of Moore’s law. An IP is not only required to work in stand-alone mode, but must also work in the context of the rest of the circuits, including other third party IPs, in a target SoC. IP integration and verification are regarded as some of the biggest challenges faced by SoC designers. The same IP operating in two different modes can experience very different voltage drops at the top level. To ensure power integrity of an IP across all levels of hierarchy in the SoC, the IP has to be accurately modeled and characterized for different modes of operation in top-level voltage drop analysis. Transfer of the IP to an SoC team must include the electrical and physical properties of the IP, along with any embedded constraints for power integrity sign-off.