Ansys PathFinder Getting Started
Ansys PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.
- Users will gain an understanding of Totem PathFinder layout-based analysis and a proficiency in both running analyses and debugging ESD-related issues using the GUI Wizard-based flow.
- Basic understanding of Ansys Totem and ESD concepts expected.
Target Audience: Chip IP/SoC/CAD Engineers & Designers
Teaching Method:Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops.
Learning Options: Training materials for this course are available with an Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.
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