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PathFinder User Training

Course Description

This tutorial will cover chip-package-system ESD analysis with ANSYS tool suites. It covers lecture and demonstrations of how to perform a systematic chip-level ESD analysis using PathFinder, a robust silicon proven solution that has been certified by several semiconductor foundries. We will review identification of HBM/MM/CDM on-chip ESD failures and root-cause analysis  using PathFinder.

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