ANSYS Totem Getting Started
Ansys Totem is a transistor-level power noise and reliability analysis platform that enables you to perform comprehensive power integrity analysis on analog mixed-signal IP and full custom designs.
Totem enables creation of IP models for SOC-level power integrity signoff using RedHawk and generates compact chip models of power delivery networks for a variety of analyses including power integrity and ESD/EMC at chip and system-level.
This course teaches the essential skills you will need to start performing basic EM/IR analysis on your own using AnsysTotem.
The course is designed to be used along with the workshop and the user is encouraged to follow along the Lecture with Totem session. Emphasis has been done to have a quick ramp up of the features using the GUI.
- Totem’s core engines for extraction, simulation, electromigration and self-heat analysis are certified for all major technology nodes and correlated several times against spice and silicon measurements. Totem is certified across several major foundries and is the preferred signoff tool for several major semiconductor companies.
- Totem supports all major data formats (GDS, OASIS, LVS database, etc.) for analog, LEF/DEF (for digital) and is compatible with all major spice simulation environments. It has capacity to handle very large designs and possesses superior macro-modeling capabilities for generating an accurate and compact IP model for SOC signoff.
- Totem provides a comprehensive suite of analyses spanning early stage to signoff. It can effectively handle a variety of design styles such as SerDes, data converters, power management IC, embedded memories, DRAM, Flash, FPGA and chip image sensors. Additionally, it delivers numerous analysis capabilities including substrate noise analysis, RDSON analysis, thermal and ESD analysis to address challenges in different designs. It also provides a configurable cockpit for customers to customize their analysis based on their workflows.
The basic understanding of the EM and IR signoff is expected.
Target Audience: Analog and Mixed Signal IC design engineers and IC layout designers.
Teaching Method: Lectures and computer practical sessions to validate acquired knowledge. A major emphasis is placed on teaching along with workshop.
Learning Options: Training materials for this course are available with an Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.
Agenda SUBSCRIBE TODAY
|Date/Time||Duration||Event Type||Location||Language||Class Cost|
March 10, 2021
9:30 - 16:30 CST (GMT +8)
|March 10, 2021||
|Live||Hsinchu , Taiwan||Chinese||660 USD||Register ›|
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