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Introduction to ANSYS HFSS 3D Layout for PCB

Overview

The ANSYS HFSS 3D Layout course for high-speed printed circuit board design focuses on layered structures using 3D Layout design type in HFSS and AEDT (ANSYS Electronic Desktop).  This course is designed for new users and will cover: Layer stackup, Layout viewing, Choices of solvers, Ports, Padstacks and hierarchy.  


Workshops include: Small differential via structures, Larger full-PCB structures and simulations and Subdesign cutouts from larger printed circuit boards. Plus, several workshops follow a realistic workflow from start to finish and include transient circuit simulation of EM (electromagnetic) models.

Learning Outcome

  • Know how to incorporate external models including IBIS models and HFSS connector models

  • Know how to configure circuits driving EM simulations hierarchically 

  • Know how to set up ports and connections to solder balls and ground planes

  • Know how to set up FEM (finite element method) analyses in HFSS 3D Layout

Prerequisites

  • No prior HFSS nor electromagnetic (EM) simulation is required, but any prior experience with HFSS EM simulation or ANSYS Designer RF circuit design, is helpful. 

  • Knowledge of high-speed digital circuit design, including S-parameters, transmission lines, and differential parts, is highly recommended.

  • Knowledge of printed circuit board design, including vias, component reference designators, and layer stackups, is valuable.

 

Target Audience: Electronic engineers working with high-speed printed circuit board (PCB) design and signal integrity.

 

Teaching Method: Lectures and hands-on simulation workshops to develop familiarity and productive skill in using HFSS 3D Layout.  A training certificate is issued on completion of the course.

 

Introduction to ANSYS HFSS 3D Layout for PCB

 

Agenda SUBSCRIBE TODAY  

Agenda :

This is a 1.5 day classroom course covering both workshops and lectures. For virtual training, this course is covered over 4 x 2 hour sessions, lectures only.


  • Live Classroom Day 1 - Virtual Session 1

    • Module 01: Introduction

    • Workshop 1: SSN Simulation

    • Simulating an HFSS 3D Layout SI example

    • Using Zoom To to find ports

    • Module 02: Visibility and Viewing

    • Workshop 2: Trace Layer Visibility

    • Layer menu settings to view traces between ground planes

    • Moving traces by specifying a new placement layer

    • Module 3: Solvers and Meshing

    • Extents and meshing

    • Solution setup

    • Workshop 3: PCB_Package_Assembly

    • Working with 3D Components in a Hybrid Simulation

    • Far field analysis of integrated antenna module on vehicle

    • Impact of antenna location on far field pattern


  • Live Classroom Day 1 - Virtual Session 2

    • Module 4: Ports

    • Wave, gap and circuit port types

    • Auto ports and automated port behavior

    • Workshop 4: BGA_Board_Cutout

    • Cutout half of PCB

    • Analyze two differential pairs

    • Module 5: Via Padstacks

    • Via padstack definitions and usage menus

    • Automated padstack behavior

    • Workshop 5.1: Differential Via Padstacks

    • Create a default padstack for a differential via structure

    • Invoke padstack behavior by labeling nets in via structure

    • Workshop 5.2: Differential Via Construction

    • Create a differential via structure in HFSS 3D Layout

    • Use cutouts in ground planes to create antipads


  • Live Classroom Day 2 - Virtual Session 3

    • Module 6: Hierarchy

    • Workshop 6.1: Differential Via Eye Pattern

    • Move an EM model for differential via into a circuit design in AEDT

    • Simulate and plot an eye diagram of the via at circuit level

    • Workshop 6.2: Differential Via TDR

    • Move and EM model for a differential via into a circuit design in AEDT

    • Simulate and plot the TDR (time domain reflectometry) reponse

    • Workshop 6.3: Connector

    • Instantiate an HFSS MCAD connector within an HFSS 3D Layout design

    • Simulate and plot differential pair S-parameters

    • Workshop 7.1: Serial Channel

    • Parameterize signal trace line widths in HFSS 3D Layout

    • Simulate with parameter sweep and plot eye diagram

    • Create a differential via structure in HFSS 3D Layout

    • Use cutouts in ground planes to create antipads

Filter By Country :
Date/Time Duration Event Type Location Language Class Cost
November 1, 2019
10:00 - 17:00   KST (GMT +9)
November 1, 2019 1 Day
Nov 1
Live Seoul , South Korea Korean 350000   KRW Register  ›

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