Chip Package Co-Analysis of Thermal-Induced Stress for Fan-Out Water Level Packaging

This paper presents an innovative co-analysis solution for thermal-induced stress of fan-out wafer level packaging (FOWLP). The reliability of FOWLP on either the fan-out package region or in the chip IDLs are of concern for loadings from large differential thermal expansions at Si chip and package/PCB interfaces and Tg (Glass Transition Temperature) effects in the dielectric materials. The dielectric layers in WLP and IDL of a chip are of weak ELK materials which are easy to develop crack at relatively low stress levels. The drastic property changes, for example, 30x change in Coefficient of Thermal Expansion (CTE) at Tg, aggravates the development of micro-flaws and the coalesce into long cracks which leads to eminent failure of the FOWLP. The approach in thermal-induced stress analysis includes the generation of thermal-aware chip power maps for multiple dies in FOWLP, the conversion of converged thermal profiles in FOWLP to thermal loadings for stress analysis, efficient model generation and analysis for Tg effect of non-linear material properties, and detailed sub-modeling of on-chip structures for thermal-induced stresses. Discussions of innovative thermal-induced stress modeling process and results extraction for a FOWLP test case are demonstrated.


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