Comprehensive On-Chip ESD Check and Potential Impact from FinFET, 3-D-IC and System-level Designs - Presentation

This session presents a comprehensive ESD static/dynamic methodology developed for pre-tapeout ESD verification, failure diagnosis, and predictive simulation of improvements. The methodology focuses on fast, full-chip static and macro-level dynamic analysis, featuring real HBM and CDM application examples. The presentation also discuss the impact of emerging technologies on ESD including 3-D-ICs, FinFETs and system-level trade-offs.
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