Thermal, EM and ESD Reliability Signoff for Next Generation FinFET Designs
This webinar highlights the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs. Providing high reliability is critical for next-generation automotive, mobile and high-performance computing applications; it can be addressed in a systematic way using Ansys reliability platforms throughout the design cycle.
Learn how Ansys solutions offer comprehensive chip-package-system thermal analysis, as well as thermal aware EM sign-off, for finFET designs. Discover how Ansys PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for human body model (HBM) and charged device model (CDM) analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and generating SoC-level ESD models for system-level ESD simulations.