Semiconductor IPs are critical parts of any system on chip (SoC) design. These IPs need to be analysed for their operational reliability, both by themselves and within the context of the SoC. A robust platform that can both analyse these IPs for reliability and generate an accurate model for SoC level verification is important. ANSYS Totem is a comprehensive transistor level power noise and reliability analysis platform for analog/mixed signal designs. Typical applications of Totem are:

  • Analysis of dynamic voltage drop on full-custom designs
  • Mixed signal designs
  • Large analog designs with hierarchical modelling
  • Early weakness detection
  • IP modeling for SoC analysis