7nm Chip Design
System on a chip (SoC) designs using 10nm and 7nm process nodes often use advanced 2.5-D/3-D packaging technology, such as InFO-WLP. According to Gartner, a leading information technology research and advisory company, designing, testing and manufacturing your next 7nm FinFET-based SoC will require massive resources: as much as $270 million and 500 man-years to bring a chip to market. To further improve power, performance and form factor, you could encapsulate such chips within an InFO-WLP package, but at the price of increasing design cost. The markets that best support the cost of design are high-end mobile and enterprise applications — and, by nature, these are highly demanding markets.
As a designer in these markets, you must design and deliver highly integrated devices that operate seamlessly and reliably for long periods of time, while reducing engineering time and cost, and ensuring “first-time” working silicon. This calls for a move away from the traditional silo-based design flow, to a chip-package-board co-simulation workflow and methodology. ANSYS Redhawk and related ANSYS semiconductor simulation products incorporate these workflows and methods to help you achieve first-time working silicon every time. ANSYS RedHawk and ANSYS Totem are certified for TSMC 7nm process node standards, support analysis of TSMC InFO packaging, and perform self-heat analysis for advanced FinFET nodes.
Multi-bit multi-height cell support