ANSYS Pathfinder Capabilities
HBM/CDM ESD Events
ANSYS PathFinder mimics human body model (HBM) and charged-device model (CDM) ESD events by propagating the zap current through the power/ground network, thereby identifying bottlenecks in the layout. By modeling the injection of current into any pad and subsequent flow of current through on-chip interconnects, the software identifies pin-clamp-pin paths that are ineffective in handling the high current present during an ESD event. It estimates current density in wires connected to those pads and checks this current density against foundry-specified limits, highlighting issues such as imbalanced connections on clamp/diode fingers and insufficient vias or metal segments that are too narrow in the ESD discharge path. Unlike DRC-based checks, PathFinder’s interconnect failure analysis provides a comprehensive way to cover every possible wire segment/via in the ESD discharge path.
PathFinder’s transient simulations using SPICE models and TLP curves at picosecond resolution offer silicon-correlated accuracy, which helps with failure analysis to minimize your design risk.
At the IP level, the software extracts the power/ground and substrate RC network and performs transient simulations. It takes in SPICE models for functional and parasitic devices (such as well-diodes) and accurately performs transient simulation at picosecond resolution with SPICE-correlated results. Clamps with snap-back behavior often have convergence issues in SPICE; PathFinder’s simulation engine is customized to handle snap-back behavior of the clamp devices to accurately model ESD device triggering and identify the stressed device junctions during ESD events.
PathFinder’s results have been successfully correlated with silicon by multiple IP vendors and customers.
Layout-Based Analysis and Root Cause Detection
As a layout-based ESD analysis and sign-off solution, PathFinder identifies layout issues and connectivity imbalances that might result in an ESD-event-induced failure. Examples include bumps not connected to any ESD clamps or clamps not hooked up to the power/ground network. By traversing every conduction pathway between any two relevant points inside the chip, PathFinder verifies connection robustness, checking electrical characteristics against foundry- or user-specified limits. You can generate pass-fail reports that can be cross-probed to the layout in the GUI.
Single Pass Simulation and Results Analysis
ANSYS PathFinder, with its integrated data modeling, extraction and simulation engine, offers an end-to end solution for ESD verification.
PathFinder enables a streamlined, single-pass-use model — reading in design data, setting up ESD rules, performing extraction and ESD simulations, analyzing root cause, and providing fix and optimization feedbacks — within a single-tool environment. The software uses industry-standard data formats, such as GDS and DEF. It gives you considerable flexibility in specifying various rules and associated parameters that are checked, enabling you to conduct a wide range of validation.
Capacity and Performance
PathFinder performs ESD integrity checks on IPs and large SOC designs with more than 100 million instances. It handles hundreds of power/ground/signal nets and performs resistance and current density checks in a single simulation. Full-chip ESD simulations can be completed in a few hours to a single day depending on size, number of metal layers, complexity of PG network, number of power/ground/signal nets and number of ESD devices. PathFinder incorporates multithreading and distributed computing options to handle ultra-large designs.
PathFinder now supports distributed processing (DMP-DB) to handle ESD analysis on ultra-large SoCs. The entire workflow, from design import to the final result, is distributed. On ultra-large designs, this accelerates the process compared to the DMP-ESD flow, in which the tool performs different ESD rules in different machines. DMP-DB is recommended for designs with more than 1 billion nodes after optimization. PathFinder supports all resistance and current density checks in the distributed mode. Only RedHawk simulation supports the DMP-DB flow.
Library to SoC-Level Analysis and Integration
Increasing current densities at sub-16nm processes and the related thermal issues increase the odds of failure due to ESD events on a chip. It is therefore critical to identify high current hotspots from the standard cell to IP and full-chip levels, and design the chip to avoid such reliability issues.
In addition to foundry-validated accuracy and comprehensive coverage of HBM/CDM events, PathFinder, with its built-in modeling capability based on the chip ESD compact model (CECM), lets you perform detailed ESD analysis at any level of a design, from standard cell to IP to full-chip.
The compact ESD model includes PG model, clamp devices and — optionally — the current signature. This enables accurate modeling and simulation to meet the highest reliability needs of your design.