Electrostatic discharge integrity: IP to SoC
ANSYS PathFinder helps you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). The analysis is performed at the layout and circuit levels to help you identify and isolate design issues that can cause chip or IP failure from charged-device model (CDM), human body model (HBM) or other ESD events.
Using layout and circuit-level analysis you can identify and isolate design issues that can cause chip or IP failure due to charged-device model (CDM), human body model (HBM) or other ESD events.
PathFinder is certified by a number of foundries as an ESD sign-off solution, giving you the assurance that the interconnect parasitic extraction, HBM/CDM ESD simulation and current-density checks on ESD discharge paths are accurate by foundry standards.
Root Cause Detection
PathFinder offers layout-based analysis and a GUI for detecting layout issues that could lead to ESD events.