Solving DC Power Distribution Problems

As supply voltages decrease and transistor count follows Moore’s law, DC power delivery is an important consideration for any electronic package or PCB design. Predicting power delivery network (PDN) performance is critical to ensure that a consumer electronic product functions as specified and meets battery life expectations.

You can predict DC power loss and voltage drop for a package or PCB using the ANSYS SIwave-DC simulation tool, then apply those results to improve layout prior to fabrication. As the industry moves toward 3-D IC, it is important to solve complete designs prior to fabrication to prevent system-level failures. ANSYS SIwave-DC can extract complete designs (including multiple, arbitrarily shaped power/ground layers, vias, signal traces, wirebonds and circuit elements) with unprecedented accuracy and speed, without requiring manual, often laborious layout partitioning. Multiple layout topologies similar to those in Figure 1 are supported: PoP, SoC, SiP, PKG on PCB.

For the example design, the Vcc power rail supplies 1.8V DC power to two CPUs (U1 and U2). The initial layout brings power from the VRM through an inductor to each of the CPUs. Vcc has only one via transition from layer 1 to layer 5. SIwave-DC finds this problem by highlighting areas of high current and large voltage drops.

Once the problematic area is located, the design engineer can perform simple what-if analyses to determine the best approach for improving the layout. In this example case, the engineer decided to improve the voltage drop by adding a metalized plane at the end of the inductor along; he also added multiple via (10 total) transitions to the power plane located on layer 5. Once the additional metal and via transitions were made, he reran the simulation to determine the impact on the PCB power delivery system.