DAC Conference Program

Designer Track- Session 4

Monday June 03, 1:30pm - 3:00pm | Location: N260

Power Bytes Delivered

4.2

3D Stacked (Foveros) SOC Power Delivery Analysis Methodology for Predictable Silicon Success

4.3

Two Different Approaches of Power Integrity Analysis and Correlate with On-chip measurement

Designer Track – Session 18

Tuesday June 04, 10:30am - 12:00pm | Location: N262

Embedded Systems, Security, and Tool-chain

18.6

A Full System Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits

Designer Track – Session 46

Wednesday June 05, 10:30am - 12:00pm | Location: N260

Technology to Accelerate Embedded Systems Time to Market / Innovative Solutions to Front-End Power Challenges

46.3

Designing Power-efficient & Safe Autonomous Driving Devices: Using Custom Techniques to Quickly Identify/Fix Hotspots at RTL

Designer Track – Session 66

Wednesday June 05, 3:30pm - 5:00pm | Location: N260

Machine Learning and Front End Design

66.6

Maximize TOPS (Tera Operations Per Second) per Watt for AI Chip using Early Power Analysis and Reduction

Designer and IP Track Poster

Monday June 03, 5:00pm - 6:00pm | Location: Exhibit Floor

123.12

Fast and Accurate Moment LVF Characterization for Advanced Technology Nodes

123.29

Comprehensive Chip-Package-System (CPS) Electrostatic Discharge (ESD) Simulation

Designer and IP Track Poster

Tuesday June 04, 5:00pm - 6:00pm | Location: Exhibit Floor

124.6

Rapid Prototyping of Dynamic Voltage Drop Using Combinations of Block Level Scenarios

124.14

A transistor level IR-drop based method to characterize an accurate and compact model of an IP for SoC level IR-EM analysis

124.15

A Fast and accurate Solution to Verify Layout Efficiency And Reliability For Power Management IC(PMIC) Design

124.23

A Novel Methodology for Fast PDN Sign-off by Slicing Long-Vectors

124.24

Early-Stage Power Check Methodology for IP Power Audit

Designer and IP Track Poster

Wednesday June 05, 5:00pm - 6:00pm | Location: Exhibit Floor

125.3

Fast and Accurate Incremental Power and Signal Integrity Analysis

125.11

Data analytics and BQM for better early stage PI approach

125.13

A rapid timing fixing methodology including impact of Voltage drop to identify real timing violations.

125.15

Power Grid Analysis For Huge Graphics Designs Using Big-Data Elastic-Compute Solution

125.23

Power Supply Noise Coupling Between Different Power Domains in a Large Programmable SoC

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