DAC 2018

Empowering Customers… Beyond Signoff

The future of connectivity is very promising — the new era of semiconductors will give rise to transformational products that will enable seamless connectivity with 5G, smarter devices with AI, next-gen mobility with autonomous vehicles and immersive experiences with AR and VR. These cutting-edge electronics systems demand the use of advanced sub-16nm SoCs and complex packaging technologies to deliver the required performance, functionality and rich user experience. ANSYS empowers customers beyond signoff by bringing the power of multiphysics simulations, big data analytics and chip-package-system (CPS) co-analyses to exceed power, performance and area goals.

Recommended presentations for:

Workshops

Leading industry experts will share their best practices using ANSYS solutions on topics that are critical to their design and methodology.

Design for power, performance and area by eliminating wasted design margins

Design for power, performance and area by eliminating wasted design margins

Design for Power Efficiency: Early RTL methodology for Chips and IPs

Design for Power Efficiency: Early RTL methodology for Chips and IPs

Accelerate SoC power signoff and make your data actionable

Accelerate SoC power signoff and make your data actionable

Multiphysics reliability signoff for chip, package and system

Multiphysics reliability signoff for chip, package and system
 

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

Best Practices Seminars


  • Production Proven Workflows for ADAS, Mobile and HPC Designs

    Production Proven Workflows for ADAS, Mobile and HPC Designs

  • Beyond Signoff - Pushing Performance Limits and Making Data Actionable

    Beyond Signoff: Pushing Performance Limits and Making Data Actionable

  • Multiphysics Reliability Signoff for Automotive and 5G Applications

    Multiphysics Reliability Signoff for Automotive and 5G Applications

  • Power Noise and Reliability Signoff for Analog-Mixed Signal Designs

    Power Noise and Reliability Signoff for Analog-Mixed Signal Designs

  • Multi Die Analysis and Chip Package System co-design

    Multi Die Analysis and Chip Package System co-design

  • Early RTL-driven Chip/IP Power Analysis, Reduction and Profiling - Best Practices

    Early RTL-driven Chip/IP Power Analysis, Reduction and Profiling - Best Practices

  • Timing and Voltage Variability

    Timing and Voltage Variability

  • Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

    Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

SoC Physical Designer:

ANSYS recommends the following presentations for SoC physical designers

Workshops
Best Practices
Mon, Jun 25, 10-12 Track 1: Design for power, performance and area by eliminating wasted design margins Mon, Jun 25, 1-2
Tue, Jun 26, 4-5
Production-proven workflows for ADAS, mobile and HPC designs
Tue, Jun 26, 10-12 Track 2: Accelerate SoC power signoff and make your data actionable Mon, Jun 25, 4-5
Tue, Jun 26, 1-2
Wed, Jun 27, 10-11
Beyond signoff: Pushing performance limits and making data actionable
Tue, Jun 26, 2-4 Track 4: Multiphysics reliability signoff for chip, package and system Mon, Jun 25, 3-4
Tue, Jun 26, 1-2
Wed, Jun 27, 2-3
Multiphysics reliability signoff for automotive and 5G applications
    Mon, Jun 25, 1-2
Tue, Jun 26, 3-4
Wed, Jun 27, 11-12
Timing and voltage variability
    Tue, Jun 26, 12-12:50
Wed, Jun 27, 3-4
Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

Analog Mixed-Signal / IP Designer:

ANSYS recommends the following presentations for AMS & IP designers

Workshops
Best Practices
Mon, Jun 25, 10-12 Track 1: Design for power, performance and area by eliminating wasted design margins Mon, Jun 25, 1-2
Tue, Jun 26, 4-5
Production proven workflows for ADAS, mobile and HPC designs
Tue, Jun 26, 2-4 Track 4: Multiphysics reliability signoff for chip, package and system Mon, Jun 25 3-4
Tue, Jun 26, 1-2
Wed, Jun 27, 2-3
Multiphysics reliability signoff for automotive and 5G applications
    Mon, Jun 25 4-5
Tue, Jun 26, 4-5
Wed, Jun 2-3
Power noise and reliability signoff for analog-mixed signal designs
    Mon, Jun 25 1-2
Tue, Jun 26, 3-4
Wed, Jun 27, 11-12
Timing and voltage variability
    Tue, Jun 26, 12-12:50
Wed, Jun 27, 3-4
Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

Chip-Package-System Designer:

ANSYS recommends the following presentations for CPS designers

Workshops
Best Practices
Mon, Jun 25, 10-12 Track 1: Design for power, performance and area by eliminating wasted design margins Mon, Jun 25, 1-2
Tue, Jun 26, 4-5
Production proven workflows for ADAS, mobile and HPC designs
Tue, Jun 26, 2-4 Track 4: Multiphysics reliability signoff for chip, package and system Mon, Jun 25, 3-4
Tue, Jun 26, 1-2
Wed, Jun 27, 2-3
Multiphysics reliability signoff for automotive and 5G applications
    Mon, Jun 25, 2-3
Tue, Jun 26, 2-3
Wed, Jun 27, 10-11
Multi-die analysis and chip- package-system co-design
    Tue, Jun 26, 12-12:50
Wed, Jun 27, 3-4
Functional Safety Analysis According to ISO 26262 2nd Edition in the Semiconductor Domain

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

RTL Designer:

ANSYS recommends the following presentations for SoC RTL designers

Workshops
Best Practices
Mon, Jun 25, 2-4 Track 2: Design for power Efficiency: Early RTL methodology for chips and IPs Mon, Jun 25, 11-12
Tue, Jun 26, 11-12
Wed, Jun 27, 11-12
Early RTL-driven chip/IP power analysis, reduction and profiling — best practices

Win a raffle prize in each workshop    |    Win a daily raffle for attending Best Practice sessions

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