Understanding Chip-Package Interaction (CPI) is critical for designers and manufacturers working on Printed Circuit Boards (PCBs). Register for our webinar to learn more about standard failure modes and how to mitigate them.
Time:
August 18, 2022
11 AM EDT / 4 PM BST / 8:30 PM IST
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About this Webinar
When designing boards and packages, manufacturers must understand the reliability risks involved in Chip-Package Interaction (CPI). Such risks influence electronics reliability across the supply chain today, including on-die, packaging, and board.Simulation has proven to be a valuable tool to address such issues, as it provides companies with detailed insights into the complex behaviors driving CPI and how to make more informed, better design decisions.
This webinar will provide examples and simulation workflows that address four standard CPI failure modes (that are typically driven by low CTE and high modulus of the silicon layers):
- Extreme Low-K (ELK) stresses
- Board Level Reliability solder fatigue due to temperature cycling
- Package warpage
- Ball Grid Array (BGA) Hot Tear
The workflows shown will discuss best practices for modeling each failure mode using specific simulation modeling techniques, including trace modeling and trace reinforcements, sub-modeling, and solder fatigue modeling within Ansys Sherlock, Workbench, SpaceClaim, and Mechanical.
Who Should Attend
Design, Mechanical, Thermal, Electrical, Reliability Engineers
Speakers
Gil Sharon