Course Image

Introduction to ANSYS HFSS 3D Layout for PCB


The ANSYS HFSS 3D Layout course for high-speed printed circuit board design focuses on layered structures using the 3D Layout design type in HFSS and AEDT (ANSYS Electronic Desktop). Designed for brand new users, this course covers layer stack-up, layout viewing, choices of solvers, ports, pad-stacks, and hierarchy. Workshops include small differential via structures, larger full-PCB structures and simulations, and sub-design cutouts from larger printed circuit boards.  Several workshops follow a realistic workflow from start to finish and several workshops include transient circuit simulation of EM (electromagnetic) models.

Target Audience: Engineers and Designers

Teaching Method: Lectures and computer practical sessions to validate acquired knowledge. A training certificate is provided to all attendees who complete the course.

Learning Path HFSS 3D Layout



Agenda :

  • This is a 1.5 day classroom course covering both workshops and lectures. For virtual training, this course is covered over 4 x 2 hour sessions, lectures only.
  • Live Classroom Day 1
    • Module 01: Introduction
    • Workshop 1: SSN Simulation
    • Simulating an HFSS 3D Layout SI example
    • Using Zoom To to find ports
    • Module 02: Visibility and Viewing
    • Workshop 2: Trace Layer Visibility
    • Layer menu settings to view traces between ground planes
    • Moving traces by specifying a new placement layer
    • Module 3: Solvers and Meshing
    • Extents and meshing
    • Solution setup
    • Workshop 3: PCB_Package_Assembly
    • Working with 3D Components in a Hybrid Simulation
    • Far field analysis of integrated antenna module on vehicle
    • Impact of antenna location on far field pattern
    • Module 4: Ports
    • Wave, gap and circuit port types
    • Auto ports and automated port behavior
    • Workshop 4: BGA_Board_Cutout
    • Cutout half of PCB
    • Analyze two differential pairs
    • Module 5: Via Padstacks
    • Via padstack definitions and usage menus
    • Automated padstack behavior
    • Workshop 5.1: Differential Via Padstacks
    • Create a default padstack for a differential via structure
    • Invoke padstack behavior by labeling nets in via structure
    • Workshop 5.2: Differential Via Construction
    • Create a differential via structure in HFSS 3D Layout

    • Use cutouts in ground planes to create antipads

  • Live Classroom Day 2
    • Module 6: Hierarchy
    • Workshop 6.1: Differential Via Eye Pattern
    • Move an EM model for differential via into a circuit design in AEDT
    • Simulate and plot an eye diagram of the via at circuit level
    • Workshop 6.2: Differential Via TDR
    • Move and EM model for a differential via into a circuit design in AEDT
    • Simulate and plot the TDR (time domain reflectometry) reponse
    • Workshop 6.3: Connector
    • Instantiate an HFSS MCAD connector within an HFSS 3D Layout design
    • Simulate and plot differential pair S-parameters
    • Workshop 7.1: Serial Channel
    • Parameterize signal trace line widths in HFSS 3D Layout
    • Simulate with parameter sweep and plot eye diagram
    • Create a differential via structure in HFSS 3D Layout
    • Use cutouts in ground planes to create antipads
Filter By Country :
Date/Time Duration Event Type Location Language Cost
2018년 11월 15일
9:00 AM - 5:30 PM   CST (GMT +8)
2018년 11월 15일 2 days
Nov 15-16
Live Shenzhen , China Chinese 4,200   RMB REGISTER  ›
2018년 11월 27일
10:00 - 17:00   KST (GMT +9)
2018년 11월 27일 1일
Nov 27
Live Seoul , South Korea Korean 300,000   KRW REGISTER  ›

문의 및 자료 요청은 아래 버튼을 클릭하시기 바랍니다. 

Contact Us