Ansys HFSS 3D Layout for PCB

Course Overview

The Ansys HFSS 3D Layout course for high-speed printed circuit board design focuses on layered structures using the 3D Layout design type in HFSS and AEDT (Ansys Electronic Desktop). This course is designed for intermediate-advanced users and includes 5 modules. It covers Padstacks, IBIS and Eye source setups, Parametric study, Package-PCB-Connector layout driven assembly (LDA), and DC IR analysis. Workshops include differential via structures, sub-design cutouts from larger printed circuit boards, and full ECAD and MCAD structures and simulations that follow realistic workflows from start to finish.



  • Prior knowledge of Ansys HFSS 3D Layout Getting Started course is required.
  • Knowledge of high-speed digital circuit design, including S-parameters, transmission lines, and differential parts is highly recommended.
  • Knowledge of printed circuit board design, including vias, component reference designators, and layer stackups is valuable. 

Target Audience:

Electronic engineers working with high-speed printed circuit board (PCB) design and signal integrity.

Teaching Method:

Lectures and hands-on simulation workshops to develop familiarity and productive skill in using HFSS 3D Layout.

Learning Path


Learning Outcome

Following completion of this course, you will be able to:

  • Work with HFSS 3D Layout via Padstack automation, Padstack definitions and usage.
  • Create differential vias, traces, and ground plane on different layers and assigning net names, boundary conditions and excitations.
  • Incorporate package, PCB and IBIS models in one environment and use the Nexxim transient circuit simulator from the layout interface of the AEDT.
  • Setup eye sources and terminations on the layout and generate eye diagrams.
  • Run parametric study to predict the performance of a PCB with manufacturing tolerance.
  • Combine MCAD and ECAD models and make sub-design cutouts at the desired extent in HFSS 3D Layout and analyze them all together.
  • Setup connector/package/board models in one environment and choose the solver. technology that is best for each simulation and run an LNA simulation on the concatenated model.
  • Setup a DC IR simulation and compute DC current and voltage distribution, plot DC IR field overlays, and export DC IR simulation results using HFSS 3D Layout.

Available Dates

Time Duration Event Type Location Language Course Cost Registration
March 08, 2021
11:00 - 13:00 EST (GMT -5)
5 Sessions
Mar 08-12
Virtual Virtual - WebEx English Subscription Only Register
March 11, 2021
10:00 - 17:00 KST (GMT +9)
2 Days
Mar 11-12
Live Seoul , South Korea Korean 700000 KRW Register

Learning Options

Training materials for this course are available with an Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.


This is a 1.5-day classroom course covering both tutorials and workshops. For virtual training, this course is covered over 6 x 2-hour sessions. 

Virtual Classroom Session 1 & 2 / Live Classroom Day 1

  • Module 1: Lecture 1 Padstacks
  • Workshop 1.1 Differential Via Padstacks,
  • Workshop 1.2 Differential Via Construction

Virtual Classroom Session 3 / Live Classroom Day 1

  • Module 2: 
  • Workshop 2.1 Package-PCB assembly and IBIS Setup

Virtual Classroom Session 4 / Live Classroom Day 1

  • Module 3:
  • Workshop 3.1 Serial Channel Performance

Virtual Classroom Session 5 / Live Classroom Day 2

  • Module 4:
  • Workshop 4.1 Connector-PCB Cutout,
  • Workshop 4.2 Package-Connector-PCB

Virtual Classroom Session 6 / Live Classroom Day 2

  • Module 5:
  • Workshop 5.1 DCIR