Joins us for an ANSYS Webinar

Leveraging Chip Power Models for System-Level EMC Simulation of Automotive ICs

18 aprile 2019

12:00 PM (EDT)

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Online

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The design of integrated circuits (ICs) for electromagnetic compatibility (EMC) is a fundamental requirement for the security and safety of automotive electronics systems. These must be tested for noise emission, electromagnetic interference (EMI) and for electromagnetic susceptibility (EMS) with intentional radio frequency (RF) disturbance. To achieve safety goals, chip power model (CPM) simulation is extended to evaluate the creation of noise from ICs and to capture the response of ICs to RF disturbance. This is done by leveraging the ANSYS chip ESD compact model (CECM) that captures the snapback current-voltage transfer characteristics of the ESD protection devices, silicon substrate coupling around the devices and also the chip-package-printed circuit board (PCB) interaction. The measurements and simulation are demonstrated with silicon test chips.

In this webinar,  Karthik Srinivasan, senior product manager from ANSYS and Dr. Makoto Nagata from Kobe University, Japan, will demonstrate how integrated circuit (IC), package and board designers can leverage ANSYS chip models in system-level simulations to meet the strict EMC requirements.

Bio of Presenters:

Makoto Nagata
Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001. He was a research associate at Hiroshima University from 1994 to 2002, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety. He was a co-recipient of the best paper awards from IEEE 3D-Test 2013, IACR CHES 2014 and IEEE APEMC 2015.

Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009), Custom Integrated Circuits Conference (2007-2009), Asian Solid-State Circuits Conference (2005-2009), International Solid-State Circuits Conference (2014-2017) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018). He was a technical program chair (2010-2011), a symposium chair (2012-2013) for the Symposium on VLSI circuits, and also a chair for IEEE SSCS Kansai Chapter (2017-2018). He is currently an associate editor for IEEE Transactions on VLSI Systems (2015).

Karthik Srinivasan
Karthik Srinivasan is currently working as a senior product manager of analog and mixed signal products in the semiconductors division of ANSYS. His work focuses on product planning for analog/mixed signal simulation products at ANSYS and field AE support. His research interest includes power estimation, power noise, reliability and thermal analysis for chip-package-systems. He joined Apache Design Solutions in 2006 and has taken on several roles as part of field AE team before taking over product management. He received a B.S. in electronics and telecommunication engineering from the University of Madras, India, and an M.S. in electrical engineering from the State University of New York, Buffalo in 2003 and 2005 respectively.