This advanced training course presents formal verification techniques applied to Ansys SCADE Suite models using Ansys SCADE Suite Design Verifier.
Ansys SCADE Suite Design Verifier is a formal verification tool to formally express and assess safety requirements, and effectively find bugs early in the development process. Ansys SCADE Suite Design Verifier automatically produces a counter-example when a proof objective is not satisfied by the Ansys SCADE Suite model under analysis. This tool can also be used to find divisions by zero operations as well as underflow/overflow errors in Ansys SCADE Suite models.
The course also offers a specific focus on writing verification properties with Ansys SCADE Suite Design Verifier.
- Formal verification in application development process with Ansys SCADE Suite
- Getting started with Ansys SCADE Suite Design Verifier
- Writing properties
- Verification with data
- Basic knowledge of formal verification methods and Ansys SCADE Suite.
Software Engineers / Verification Engineers
Lectures and computer practical sessions to validate acquired knowledge. A training certificate is provided to all attendees who complete the course.