As semiconductors move into the wafer-scale chip and chiplet era, there is increased focus on the power thermal and reliability area. One of the key aspects of reliability is ESD. While this phenomenon is understood at a higher-level, comprehending chip failures due to ESD and addressing them is still an extremely challenging and time-consuming task. ESD sign-off was traditionally done by experts and mask designers visually checking the layout. With the introduction of Ansys PathFinder about a decade ago, Ansys revolutionized ESD analysis and sign-off.
Now we are launching our next-generation ESD analysis solution, Ansys PathFinder-SC, which redefines ESD sign-off. PathFinder-SC is built on Ansys SeaScape, the world's first custom-designed, big data architecture for electronic system design and simulation. Its underlying highly scalable elastic compute architecture, along with big data analytics, enables you to load the largest designs within seconds.
In this webinar, we will cover how Pathfinder-SC enables ESD analysis and debug on ultra-large SOCs. We will also demonstrate advanced features in Pathfinder-SC that provide increased coverage to perform ESD sign-off with confidence.
Speaker: Karthik Srinivasan , Director Product Specialist, Ansys
- Latest advances in ESD analysis and debug sign-off technology for large SOCs
- How to speed ESD analysis with elastic scaling into the cloud
- How to increase ESD analysis coverage for greater reliability