ANSYS PowerArtist

Comprehensive RTL design-for-power platform: analyze, debug, reduce

ANSYS PowerArtist is the comprehensive design-for-power platform of choice of all leading low-power semiconductor design companies for early RTL power analysis and reduction. PowerArtist enables you to perform physical-aware RTL power budgeting, interactive debugging, analysis-driven reduction, efficiency regressions and profiling of live applications, while also enabling a seamless RTL-to-physical methodology for power grid integrity.

Power efficiency is paramount in semiconductor design. RTL designers working on a variety of applications, from mobile and CPUs to networking and automotive ICs, use ANSYS PowerArtist to analyze and reduce power early in the development cycle for the highest impact. Compared to traditional gate-level methodologies, PowerArtist provides rapid turnaround on multimillion instance designs, and enables early power-related design decisions. In order for these early design decisions to be reliable, PACE (PowerArtist Calibration and Estimation) technology delivers consistent RTL power accuracy and identifies reduction opportunities through unique modeling of physical implementation, including clock tree and mesh networks, wire capacitance and glitch.

PowerArtist automatically identifies block and instance-level sequential and combinational power reduction opportunities across clock network, data path and memory architectures to meet aggressive power targets. Using a powerful interactive graphical debug environment, RTL designers (especially those new to power) can easily and efficiently debug power hotspots. PowerArtist’s clock gating and power efficiency metrics and TCL interface for custom queries enable rigorous tracking of power through regression methodologies.

PowerArtist provides industry’s fastest power profiling capability, which can analyze activity of live applications comprising tens of milliseconds within hours — several orders of magnitude faster than traditional approaches. In addition, PowerArtist’s activity streaming and critical-signal interfaces with emulators cut the time to power by an order of magnitude. Quickly isolating a power-critical subset from millions of RTL cycles of activity, PowerArtist generates a unique RTL Power Model that interfaces with ANSYS RedHawk and delivers a seamless RTL-to-physical power methodology for early power delivery network planning and sign-off.


Physically-Aware RTL Power Budgeting

Make reliable design decisions early with unique PowerArtist PACE™ technology that models physical effects, such as clock distribution, for consistent RTL power numbers versus post-layout.

Comprehensive Power Analysis and Exploration

Identify power hotspots and quickly debug their root cause with an intuitive graphical interface and custom queries into the database with a powerful Tcl interface.

Analysis-Driven Automated Power Reduction

Reduce clock, memory and logic power with high-impact block-level and instance-level RTL techniques based on production-proven foundation power analysis technology.

Power Profiling and Budgeting for Real Applications

Generate RTL power profiles of system application-level activity scenarios, such as OS boot up, orders of magnitude faster, and avoid late and costly surprises.

Regressions Based on Power Efficiency Metrics

Prevent power creep through regular and rigorous monitoring of power and power efficiency metrics throughout your design development cycle.

RTL-Driven Power Grid Integrity

Perform early power grid prototyping and increase sign-off coverage by focusing on peak and di/dt cycles rapidly located by PowerArtist RTL Power Model, and used by ANSYS RedHawk directly.

See how our customers are using our software:


Optimizing Processor Power-to-Performance: AMD

This webinar underscores AMD’s RTL power regression methodology that made it possible to significantly reduce power consumption on processor designs. Rigorous tracking of power over multiple bandwidth scenarios led to 70 percent idle power reduction and 400 percent improvement in power-bandwidth slope. View Case Study

Automotive Radio Interference Reduction: NXP

NXP presents their use of low power optimization at RTL with ANSYS PowerArtist to reduce radio interference of digital logic for an automotive infotainment application. View Case Study
ST MIcro

Power Methodology for ARM-based Subsystem: ST MIcro

This webinar focuses on a high-performance ARM-based subsystem within ST, and the challenges and benefits of estimating and reducing power early in the implementation flow. Results include benchmarking of ANSYS PowerArtist’s RTL power accuracy versus sign-off numbers. View Case Study