ANSYS PowerArtist Capabilities
Physically-Aware RTL Power Budgeting
Early power analysis enables you to make high-impact design decisions. But the more advanced the process node, the greater the influence physical design considerations have on power. This can lead to greater variation in power estimation between RTL and post-layout gate-level stages of your design process. There is no guarantee that RTL changes to reduce power will carry through your physical implementation because of that growing gap.
PowerArtist models key physical design considerations at RTL including clocks, glitches and wire capacitance. PowerArtist Calibration and Estimation (PACE) is a pioneering technology that provides consistent accuracy of RTL power versus gate-level sign-off power numbers — all while ensuring rapid turn-around time for multimillion gate-equivalent RTL power analysis. High-performance engines and simple, streamlined usage flow provide RTL power estimates in minutes, compared to the hours it might take you before the gate-level netlist and the corresponding power numbers are available.
PACE creates a feedback loop between physical and RTL design processes to ensure accuracy and consistency of RTL power estimates. It extracts key power-related physical design information missing at RTL, including clock tree and gating, wire capacitance and cell distributions. As an RTL designer, you also benefit from an easier setup. PACE automates the characterization and calibration of physical modeling during RTL power analysis, and you are not required to manually translate physical considerations into RTL constraints. Clocks, in particular, pose a challenge — they consume a significant portion of the overall power although they are primarily described as an ideal net in RTL source code. PACE incorporates an advanced RTL clock tree synthesis engine for both mesh and tree topologies, and has been proven to achieve out-of-the-box RTL clock power within 10-15 percent variation of sign-off for advanced FinFET technologies.
Comprehensive Power Analysis and Exploration
Time-to-market and first silicon success are critically important for design teams. Early awareness of power and power bugs plays a vital role in meeting these goals. PowerArtist’s industry-leading RTL power analysis provides comprehensive capabilities to enable early power budgeting and efficiency with average and time-based power analyses. Fast runtimes enable effective evaluation of multiple architectures for power efficiency. Unlike a sea-of-gates view after synthesis, PowerArtist’s RTL inferencing engine retains a functional view, making it easy to identify and debug power hotspots.
Power is broken down by category, hierarchy, power and clock domains. Whether you are identifying power hotspots in a design, or power exploration using clock gating or power gating techniques, or understanding peak versus average power, PowerArtist allows you to perform fast what-if and quick root cause debug analyses with its detailed textual reports, GUI and TCL-based interfaces.
PowerArtist graphical interface is a best-in-class power debug platform. Using PowerArtist’s feature-rich GUI environment, RTL designers can explore power consumption and identify areas of potential improvements. They can study which part(s) of the designs are consuming more power than expected, identify possible solutions and undertake fixes. Interactive cross-probing between power-annotated schematic views and powerful sort, search and filter capabilities enable descending to any level of hierarchy/submodule and query on dynamic vs. leakage power, reduction opportunities sorted by savings and other metrics.
PowerArtist’s TCL-based interface to its power database enables you to automate custom queries and go beyond the standard tool reports. You can quickly traverse the design and access detailed power and activity properties and metrics across design categories and design hierarchies. Whether you are designing a graphics processor and are concerned about glitch-prone logic, or a mobile application trying to optimize clock gating efficiency of every flop, or a networking application optimizing memory accesses, the comprehensive TCL interface enables you to present data in a way that is most effective for your needs.
Analysis-Driven Automated Power Reduction
Power is at the forefront of semiconductor design. Whether it is a handheld battery-operated device, a high-performance networking application or a cost-effective IoT design, power efficiency is a critical requirement. Early design decisions can reduce power consumption, but they need to be based on predictable analysis. PowerArtist identifies reduction opportunities based on a complete evaluation of the change in logic and activity in the context of physical effects. This analysis-driven approach to power reduction enables you to focus on the right low-power RTL changes, and ensure that power savings do not disappear during the implementation phase. The figure below underscores the pitfalls of blind automation. It plots cumulative power savings for an application processor against RTL reductions. Of the approximately 300 RTL power reduction opportunities identified, the top five were sufficient to realize half of the identified savings.
PowerArtist’s reduction engine identifies all wasted activity in the design including clocks, memories and datapath logic. Using combinational and sequential techniques that complement downstream tools, PowerArtist automatically identifies a wide range of RTL changes that reduce power at both block level and leaf instance level. PowerArtist identifies missed opportunities for block level clock and data gating for high power savings. It can also add and improve clock gate enables for sequential instances, ensure memory accesses are not redundant and shut off cones of logic when not needed. Unlike approaches limited by the number of sequential stages, PowerArtist’s high-performance architecture analyzes reductions across all sequential stages and runs fast, enabling quick what-if analysis. Depending on your preferences, PowerArtist automatically generates power-optimized RTL and synthesis constraints, or guides you through a manual RTL rewrite process.
The figure shows how 50 percent savings in power can be achieved with just a few RTL changes.
PowerArtist’s reduction methodology goes beyond automated reduction techniques with an interactive graphical and Tcl-based power exploration framework that have been proven to be highly effective in identification of large power-saving opportunities.
Power Profiling and Budgeting for Real Applications
Traditional methodologies for power are based on design activity simulated for a few microseconds, potentially putting the design at risk from power issues that can be exposed by real-life stimuli. Yet, computing power waveforms for such scenarios as operating system boot-up and high definition video frames is impractical, and can take days to weeks with standard power analysis tools and methodologies. Activity analysis is often used as a faster alternative, but it can miss power-critical events. Activity does not always translate directly to power, especially at RTL when design implementation details are missing. PowerArtist provides various capabilities to address these challenges.
PowerArtist’s power profiling is a unique capability that makes it possible to analyze system-level vectors encompassing tens to hundreds of milliseconds of design activity. Designed specifically for long vectors, PowerArtist’s power profiler runs several orders of magnitude faster compared to traditional approaches that compute cycle-by-cycle power waveforms. Power profiles adequately model synthesis effects such as clock gating and physical effects such as clock tree modeling in order to create an accurate representation of the power profile for pre-layout designs.
In addition, PowerArtist provides efficient flows to process activity from emulators. By focusing on power-critical signals, the time taken to generate and consume FSDB/VCD files is significantly reduced with a minimal loss of accuracy. PowerArtist PAVES further accelerates the turnaround time by an order of magnitude by directly streaming in emulator-generated activity for power analysis, eliminating the inefficiencies associated with large FSDB/VCD activity dump files.
Power profiling for system-level application vectors provides several benefits. Power-critical blocks identified through RTL power profiling enable early high-impact design decisions in order to reduce power consumption. Power profiling also enables power-critical and thermal-critical window identification for early power grid integrity analysis in ANSYS RedHawk. Going beyond the chip, RTL power profiles over long durations also enable Chip Power Model creation for early chip-package-system power and thermal integrity analyses.
Regressions Based on Power Efficiency Metrics
Power is a critical requirement for a chip, whether the need is to extended battery life, reduce the cooling budget or lower chip cost. It is therefore important to identify and eliminate power bugs at every stage of a chip and system design. The earlier the identification, the lower the cost, and the faster the time-to-market. Power regressions are very effective in guarding the design against an undue increase in power, similar to their functional counterparts.
PowerArtist provides a complete regression framework with well-defined power metrics and data mining utilities to track power efficiency and help you isolate power bugs. A commonly used power efficiency metric is clock gating efficiency (CGE). In addition to static CGE that predicts the gated bits ahead of synthesis, PowerArtist computes cycle-accurate dynamic CGE as a measure of clock cycles that are not gated when data is stable. PowerArtist memory power efficiency metrics track redundant read and write accesses. Power efficiency metrics are available at different abstractions as relevant to that metric; for example, CGE metrics are reported per flop, per clock gate, per hierarchical block and per clock domain. An important requirement for a regression framework is a power database that allows custom queries to search and compare data across design versions. PowerArtist’s TCL interface to its power database is intuitive and extensive. PowerArtist utilities compare and plot power metrics across design versions, and can be used to accelerate deployment of customized power regressions.
Power regressions have been widely adopted as a methodology, while the RTL is under development and also during late-breaking functional ECOs. Design teams competing on power are routinely running block-level and chip-level regressions using PowerArtist to meet their power goals.
RTL-Driven Power Grid Integrity
Power-efficient design is about more than lowering power — it is about ensuring power and thermal integrity of a chip, its package and the system. With noise margins rapidly dropping at advanced process technologies, a power delivery network (PDN) is further challenged in delivering the required power under all scenarios. Low power techniques exacerbate the power noise issue since they result in larger di/dt swings as the design switches between low and high power states. It is important to account for such power-critical activity scenarios early during the PDN design phase. However, gate level simulations are available late with limited coverage. Besides, physical tools are not designed to analyze long vectors.
PowerArtist scans through millions of RTL cycles of activity much faster than physical analysis tools to automatically focus on power-critical scenarios for subsequent power delivery network analysis. It generates an RTL Power Model (RPM) focusing on peak and di/dt scenarios along with additional power data. RPM can then be directly read by ANSYS RedHawk for early PDN prototyping when physical design data for blocks is not ready, and for increased sign-off coverage. Using RPM, ANSYS RedHawk can also generate an early Chip Power Model (CPM), enabling early chip-package co-design.
RPM enables a seamless RTL-to-physical flow with a model-based handshake between system houses and ASIC vendors, or even within two teams in the same company.