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Ansys RedHawk
Getting Started

Course Overview

This hands-on course is designed for new or current RedHawk users who may want to refresh their skills or get training on the following topics:

  • RedHawk flow overview, including how to debug designs using RedHawk Explorer
  • Static IR/EM analysis including ‘What-If’ analysis
  • Dynamic Vectorless/VCD analysis
  • Introduction to advanced topics such as Chip Package Co Analysis (CPA), Distributed Machine Processing (DMP) and Chip Power Model (CPM) generation

Target Audience

Chip IP/SoC/CAD Engineers & Designers

Teaching Method

Self-paced slide presentation and computer practical sessions to validate acquired knowledge. Emphasis is placed on tool background & methodology as well as workshops.

Learning Path

Currently, no Learning Path available

Learning Outcome

Users will gain an understanding of RedHawk modelling and flows, as well as a basic proficiency of how to run the tool for different analyses.

  • Basic understanding of IR and EM sign off is expected.

 Available Dates

Currently, no training dates available

Date / Time Duration Event Type Location Language Course cost Registration
May 19, 2021
09:30 - 16:30 CST (GMT +8)
1 Day
May 19
Live Hsinchu, Taiwan Chinese 19500 TWD REGISTER
September 8, 2021
09:30 - 16:30 CST (GMT +8)
1 Day
Sep 8
Live Hsinchu, Taiwan Chinese 19500 TWD REGISTER

Learning Options

Training materials for this course are available with a Ansys Learning Hub Subscription. If there is no active public schedule available, private training can be arranged. Please contact us.

 

Agenda

This is a 1-day classroom course covering both lectures and workshops. For virtual training, this course is covered over 2 x 2-hour sessions lectures only.

Virtual Classroom Session 1

  • Agenda (Module 1)
  • Module 2 – Basic Overview
  • Ecosystem/Design Flow
  • Data Requirements & Modeling
  • Module 3 – Static Analysis
  • Workshop 1
  • Static Analysis
  • Static & Electromigration analysis
  • Module 4 - Static Explorer
  • Data Integrity, Design Weakness, and Hotspot analysis

Virtual Classroom Session 2

  • Module 5 – Dynamic Analysis
  • Vectorless Analysis
  • Results, Reports, and Maps
  • Using TCL commands
  • Workshop 2
  • Dynamic Analysis
  • Module 6 –Dynamic Explorer
  • Module 7 – Advanced Topics
  • VCD Based Analysis
  • Package Handling
  • Distributed Machine Processing (DMP)
  • Chip Power Model (CPM) Generation
  • Workshop 3
  • Early analysis, SignalEM analysis, Low-power analysis
  • CPM generation
  • Thermal analysis

Virtual Classroom Session 1 / Live Classroom Day 1

  • Agenda (Module 1)
  • Module 2 – Basic Overview
  • Ecosystem/Design Flow
  • Data Requirements & Modeling
  • Module 3 – Static Analysis
  • Workshop 1
  • Static Analysis
  • Static & Electromigration analysis
  • Module 4 - Static Explorer
  • Data Integrity, Design Weakness, and Hotspot analysis

Virtual Classroom Session 2 / Live Classroom Day 1

  • Module 5 – Dynamic Analysis
  • Vectorless Analysis
  • Results, Reports, and Maps
  • Using TCL commands
  • Workshop 2
  • Dynamic Analysis
  • Module 6 –Dynamic Explorer
  • Module 7 – Advanced Topics
  • VCD Based Analysis
  • Package Handling
  • Distributed Machine Processing (DMP)
  • Chip Power Model (CPM) Generation
  • Workshop 3
  • Early analysis, SignalEM analysis, Low-power analysis
  • CPM generation
  • Thermal analysis