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Variability-aware and SPICE-accurate Timing Closure

Many sources of on-chip variation are conspiring to kill your project. Learn how the ANSYS FX platform with its unique variation-aware technology can save you from gross inaccuracies in modeling variation. Important topics include SPICE-accurate process variation especially at low voltage; SPICE-accurate voltage variation including clock jitter due to IR drop; and a methodology shift in modeling chip-level aging that is easier faster and more accurate than current approaches.

Speaker Bio:
Brett Yokom is an experienced EDA professional with 11+ years of experience.  He joined ANSYS in September of 2013 and is currently Lead Technical Project Manager for FX technologies.
Brett started his career at IBM working on both front-end and back-end design for custom clocks and timing closure. As a part of ANSYS Brett has been guiding customers with timing variation adoptions of FX technologies including Liberty Variance Format (LVF) Constraint Uncertainty and Path FX.


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