ANSYS Totem Capabilities
Early and In-design Analysis
In analog and mixed-signal designs, EM and IR analysis is often considered as close as possible to tape-in. This is due to fundamental limitations in the traditional workflow which requires the design to be LVS clean to perform extraction, simulation and achieve reliable EMIR results. However, as design cycles shrink, there is an increasing need for in-design analysis in the early stages of the design process. This is due to technology scaling which leads to thinner interconnects exhibiting higher parasitic resistance, lower EM tolerance, higher power density and lower operating voltages.
Totem offers a variety of capabilities like power grid weakness analysis, missing vias, P2P checks and variety of early stage static and dynamic IR and EM analysis that can highlight design weakness which are costly to address closer to tape-in. These are presented in an intuitive and user-friendly manner for designers to make key design decisions such as power grid planning, bump placement, decoupling cap optimization, EM on critical nets, etc.
It is a challenge to select the correct vectors for stressing the power grid, so designers may often run longer simulations to cover more scenarios. Including power grid complexity in the overall simulations increases the analysis time considerably in traditional flows which consumes several days to weeks. This renders any ECO changes impossible and may lead to costly metal re-spins or even silicon yield issues.
Totem offers a variety of options to enable an accurate signoff of large, mixed-signal designs. Key features like native handling of the place and route digital database and hierarchical analysis of complex AMS vastly simplifies the overall flow by facilitating a bottom-up rollup view where block owners can perform a thorough validation of their blocks and rollup a comprehensive multi-state transistor level or abstracted macro-models for top- level analysis. While integrating several blocks along with digital place and route data, the top--level simulations can leverage and align different functional states of sub-blocks to mimic several worst case scenarios that can stress the power grid.
A classic example of complex mixed signal interface is a PHY interface. The Serial interfaces (a.k.a SerDes) can be broken into well defined sub-blocks like clock and data-slices. These can be analyzed and modeled as macro-models. These macro models can retain complete un-reduced power grid down to the device diffusion and detailed multi-state current profiles modeling different functional states. Moreover any digital blocks in the interface can also be modeled in detailed down to standard cell level w/ Vectors(VCD/FSDB) or with vectorless approach. Full IP level analysis entails combining these clock and data slice views and including package models to perform a detailed transient voltage drop analysis. Totem analyzes noise propagation through the entire power delivery network, from the package to the on-chip power grid and substrate network. Validation of Totem’s simulation results against silicon by various customers speaks to its accuracy.
Advanced Reliability Analysis
While FinFET offers several advantages with respect to area, performance, local thermal gradients on FinFET designs can reach temperatures as high as 30 degree Celsius on the device, which is mainly due to the 3D nature of the FinFET’s, ultra-thin, highly resistive interconnects and dielectrics that produce poor thermal conductivity. Totem provides a comprehensive EM signoff which includes power/signal EM analysis, modeling joule-heating, wire coupling and self-heating of the FinFETs and their impact on the interconnects. The flow has been enabled by all major foundries and used by all customers doing FinFET designs. Statistical EM Budgeting is also enabled in Totem to address demands for automotive and other mission critical applications.
IP Signoff and SoC Integration
IPs are integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs beyond the predictions of Moore’s law. An IP is not only required to work in stand-alone mode, but must also work within the context of all the circuits, including third party IPs, in a target SoC. IP integration and verification are regarded as some of the biggest challenges faced by SoC designers. The same IP operating in two different modes can experience very different voltage drops at the top level. To ensure power integrity of an IP across all levels of hierarchy in the SoC, the IP has to be accurately modeled and characterized for different modes of operation in top-level voltage drop analysis. Transfer of the IP to an SoC team must include the electrical and physical properties of the IP, along with any embedded constraints for power integrity signoff.
Totem’s GUI environment is tightly coupled to the underlying engine and offers advanced query and debugging capabilities to easily identify and root-cause design weakness. It has several customizable maps and debugviews that can help designers easily find and fix the real design weakness. Moreover, Totem also offers capabilities to perform what-if analysis to perform quick design fixes and perform verification before finalizing the changes in the design. This significantly speeds up the turnaround compared to traditional flows where one needs to perform design fixes in implementation tools and then perform expensive LVS and RC extraction before performing the EMIR analysis. Totem’s versatile, multifunctional GUI gives the look and feel of a layout editor while providing full visibility into simulation results through sophisticated multi-tab and multi-pane capabilities.
Advanced Analysis and Modeling
Totem offers advanced analysis and modeling for a variety of markets. This includes analysis such as:
- Automated comprehensive thermal aware EM validation of standard cell library and thermal view generation for SOC level analysis
- RDSON and EM signoff for large, complex RF and power management IC
- Substrate noise coupling analysis for high-speed AMS/RF and PMIC designs
- ESD analysis for comprehensive HBM and CDM signoff
- Chip-package-system power and thermal analysis
- Multi-die power integrity signoff