According to Gartner, designing, testing and manufacturing 7nm FinFET-based system on a chip (SoC) requires massive resources: as much as $270 million and 500 man-years to bring the chip to market. Encapsulating such chips within a 2.5/3D package such as InFO-WLP improves power, performance and form factor while increasing the cost of design. To make a profit on that level of investment, the market for these chips tend to be high-end mobile and enterprise applications. To satisfy customer needs in these demanding markets, design teams have to deliver highly integrated devices that operate seamlessly and reliably for long periods of time. Additionally, you have to reduce the engineering time and cost, and ensure “first-time” working silicon. To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology.
By leveraging chip-package-system flows and methodologies to target 7nm technologies, you can achieve faster design convergence along with considerable business advantages. You can additionally profit from the reduced power consumption, higher speed and density improvements available from the 7nm process node. Such simulation flows and solutions have to meet two broad requirements to make a meaningful impact: they must provide multiphysics sign-off accuracy and coverage, and enable accelerated design closure and optimization.
For 7nm designs, increased investments, higher levels of integration and considerable market expectations bring extra scrutiny on the accuracy and validity of the simulation results. For example, meeting a 15 percent voltage drop limit in a 7nm design running at 500mV is extremely challenging — the accuracy of the predicted results become extremely important when making design trade-off choices that affect die-size, schedule and performance. Similarly, validating a design for electro-migration (EM) and ESD sign-off require careful modeling of advanced extraction and foundry rules both in an N7 chip and its InFO-WLP package. The focus on accuracy needs to cover seemingly disparate areas like register-transfer level (RTL) power prediction, which in turn drives power regressions, power profiling and comprehensive power budgeting. Accuracy is important not just at the chip level but across the entire chip-package-board/system level to foster confidence in design trade-off decisions, which in turn affect schedule, cost and ability to meet specifications. Hence for 7nm, chip-package-system co-simulation workflows need to deliver accurate multiphysics modeling and across power, timing, stress, temperature and reliability analyses.
Given the cost implications of failure, you must be supremely confident in the ability of the chip and its associated system to perform according to specifications before going to silicon and subsequent volume production. Simulation “coverage” across a broad spectrum of physics that affect power, performance, functionality and reliability of these complex devices is needed to make such decisions. Traditional power noise analysis methodologies are limited to few sets of ”worst-case” scenarios, so many of the combinations possible in a multicore 7nm design go without being simulated at all.
The ability to profile, score and rank switching scenarios not only from a power perspective but from their ability to create local and/or global rail collapse is crucial to get the desired sign-off confidence. These scenarios need to be driven both by VectorLess and known use cases (gate vectors, RTL, emulation) to provide as complete a coverage as possible. Such focus on coverage needs to expand to reliability, signal integrity and other sign-off checks as well. For example, reliability analyses need to span local self-heat analysis, global chip- package thermal-aware EM/ESD analyses and system-level cooling analyses. In addition, signal integrity analyses need to expand beyond traditional “SI” or cross-talk focus to include coupling of power rail and signal noise to predict jitter and noise coupling both inside and outside the chip to meet stringent DDR, SerDes specifications.
InFO-WLP packages, given their bandwidth and form factor benefits, are the norm for N7-based chips. However, complex and irregular geometry structures in these package technologies require enhanced modeling flows. Given the tight coupling between the package and one or more chips inside the package, co-simulation, co-debugging and co-optimization are a “must-do” than “nice-to-do.” Simulation workflows must include the extraction and simulation of the chip(s)-package system together for power, signal, reliability (EM, ESD) and thermal/stress modeling and sign-off.
The primary use of N7 devices are for high-end time-sensitive markets like mobile and enterprise (networking, etc.). Faster convergence is key to meet and beat design schedules that are increasingly aggressive. To deliver against such expectations, flows targeted for these designs need to meet two key conditions: distributed scalable (or elastic) performance with broad sign-off coverage with turn-around time of hours (not days) for the most complex and largest designs, and drive closer collaboration and data exchange between design and various simulation workflows through flexible and rapid data analytics. Such capabilities reduce design cycles considerably by enabling multiple design iterations within a single day instead of weeks and allow design teams to target their fixes by simultaneously looking at multiple design variables – this in turn leads to optimized die sizes, package elements and lower system costs without sacrificing performance.
In subsequent blogs, I will expand on these topics separately and highlight how N7 and InFO-WLP package-based designs can benefit from ANSYS solutions that enable the above requirements.