Variability has become the new enemy in 7nm FinFET designs. You can’t fix what you can’t find, and variability takes many forms (e.g., voltage drop, temperature, process). Increased cross-coupling of various multiphysics effects such as timing, power and thermal in 7nm designs poses significant challenges for design closure. Traditional solutions using margin-based methodologies are inadequate. Increased variability makes it hard to predict true silicon behavior and impacts both time-to- result (TTR) and time-to-market (TTM) goals in complex design projects.
Attend this webinar to learn how ANSYS multiphysics simulations can address the different forms of variability and their impact on performance. With an understanding of the true limits of built-in margins, you can achieve the target maximum frequency on silicon, while drastically improving the functional yield of your chips.
Dr. Joao Geada is a chief technologist at ANSYS, with over 20 years of EDA experience. He leads the development of the semiconductor business unit’s FX timing and timing variation products. He is the author of numerous papers and patents around static timing analysis and statistical timing. Before ANSYS, Dr. Geada was CTO and co-founder of CLK Design Automation and one of the lead architects in the verification and simulation group at Synopsys. Before Synopsys, Dr. Geada was a senior researcher at Cadence Design Systems and started his career at the IBM TJ Watson Research Center. Dr. Geada holds a Ph.D. and bachelor’s degree in engineering from the University of Newcastle on Tyne (UK).