Managing IP Risks

By Karthik Srinivasan, Corporate Applications Engineer Manager, Analog Mixed Signal, ANSYS

IP-aware SoC power noise and reliability analysis workflow is required in the FinFET era.

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IP and SoC designers may have different expectations with regard to the conditions for final sign-off.

One of the biggest benefits of system-on-chip (SoC) designs is that they are modular and build upon previously validated intellectual property (IP) components, either developed in-house or purchased from external sources. This approach enables SoC engineers to quickly create new designs and shorten time to market. But, because engineers who are designing the individual components are often not the ones who are designing the SoC, challenges arise during full-chip verification. The IP and SoC designers may have different expectations with regard to the conditions for final sign-off. If the gap in expectations is large, it can create design issues that affect the final product’s performance, functionality and release date.

IP engineers often validate their designs as if each component were operating in near-ideal conditions. SoCs are verified and signed off with mainly abstracted or, in many cases, black-box views of the IPs. However, as more and more high-speed and noise-sensitive components get placed next to each other, or next to the core, digital logic failure conditions emerge that once were not considered. This worsens when these IP components share one or more power and ground supply domains. For example, when a bank of high-speed DDR interfaces is placed next to a bank of memory, the switching of the DDR can generate sufficient noise on the shared ground network to adversely affect memory operation. 

As designs migrate to smaller silicon technology nodes, especially 3-D transistors or FinFET, differing design goals for IP and SoC designers will adversely affect power noise and reliability.

SoC architecture
Typical SoC architecture with multiple IPs
IP power noise environment
Requirements for a successful IP power noise verification environment

When the supply voltage is scaled down from 1+V levels to the sub-700 mV range, fluctuations that had been between 5 percent and 10 percent increase to about 15 percent to 20 percent because of a combination of higher peak current, increased current density and reduced supply voltage levels. Thus, the impact of power noise becomes more significant for FinFET-based designs than in earlier technology. Accurate prediction of these fluctuations in the power and ground network is critical to ensure that IP components continue to operate as designed in the full-chip context. The traditional divide-and-conquer approach of over-design doesn’t work when on-chip resources become scarcer and noise coupling increases due to the presence of multiple voltage islands. Design and verification of IP components for power noise immunity requires a two-step approach.

Layout-based design analysis

As a first step, the IP itself needs to be simulated extensively during the design process to ensure that the power distribution network and signal interconnects are as robust as possible. For this particular step to be successful, the methodology should be applicable to any type of component but with some differences based on each type. In addition, the approach must support many different analyses and needs within a single environment; these include static and dynamic power noise modeling, substrate guard ring design verification, power- and signal-line electromigration sign-off, and electrostatic discharge integrity verification. Because of the customized nature of these designs, the simulation environment should be layout driven. In contrast to typical SPICE-based simulation approaches that are difficult to analyze, the results should be overlaid on the layout to enable quick in-design fixing and iteration.

A layout-based approach highlights design weaknesses quickly through static and dynamic simulations. The connectivity and static IR simulations must be performed early in the design process to identify and fix gross grid issues. As the design matures, dynamic voltage drop analysis can be used to isolate specific areas of the design that are likely to fail from simultaneous switching.

The simulation environment should be SoC-aware so that the IP designer can include the impact of the SoC-like switching noise coupling, power-ground grid impedance and package parasitics easily into runs without compromising the turnaround time and required simulation efficiency. An ANSYS-based framework can enable such an SoC-aware IP analysis and sign-off methodology.

Layout-based power and reliability verification from early phase to sign-off for custom and analog IPs. This approach highlights design weaknesses quickly through static and dynamic simulations
Layout-based power and reliability verification from early phase to sign-off for custom and analog IPs. This approach highlights design weaknesses quickly through static and dynamic simulations
Layout-based power and reliability verification from early phase to sign-off for custom and analog IPs. This approach highlights design weaknesses quickly through static and dynamic simulations
SoC methodology
SoC-aware IP analysis and sign-off methodology.

Accurate models with embedded rules

The second step involves creating accurate, representative and compact models of the IP component that not only capture the physical and electrical attributes but also incorporate embedded rules. These models can be plugged into the SoC analysis to ensure that the IP obtains a robust power-ground connection and model its impact on other parts of the design. The embedded rules provide a straightforward mechanism to check whether or not the connectivity of IP at the SoC level meets the expectations of the designer.

Accurate prediction of fluctuations in the power and ground network is critical to ensure that IPs continue to operate as designed.

As designs move to 14 nm technologies based on FinFETs, power noise and reliability become the top concerns. This is especially true for IP components, as they involve multiple parties and design steps leading to increased chances of failure. Having a robust validation methodology that also incorporates a model creation and model use framework using ANSYS Totem and ANSYS RedHawk will enable both IP and SoC designers to meet future challenges.

Full chip sign-off with accurate IP macro models

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