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High Capacity Power Signoff Using Big Data - Webinar

In this webinar, learn how NVIDIA has developed a workflow to run a flat, full-chip power integrity and reliability signoff analysis using a fully distributed compute and big data solution with ANSYS RedHawk-SC. They achieved a turn-around time of well under 24 hours for full-chip flat power signoff analysis on NVIDIA’s largest GPU – Volta, which contains around 21 billion transistors. Additionally, silicon correlation exercises performed on the Volta chip using RedHawk-SC produced simulated voltage values that were within 10 percent of silicon measurement results. This methodology was published in the Design Automation Conference 2017 (DAC 2017) Designer/IP track poster session. Discover how NVIDIA’s most powerful GPU uses ANSYS’ next generation SoC power signoff solution based on big data to deliver the best performance for cutting-edge AI and machine learning applications.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk


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Thermal, EM and ESD Reliability Signoff for Next Generation FinFET Designs - Webinar

This webinar highlights the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs. Providing high reliability is critical for next-generation automotive, mobile and high-performance computing applications; it can be addressed in a systematic way using ANSYS reliability platforms throughout the design cycle.

Learn how ANSYS solutions offer comprehensive chip-package-system thermal analysis, as well as thermal aware EM sign-off, for finFET designs. Discover how ANSYS PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for human body model (HBM) and charged device model (CDM) analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and generating SoC-level ESD models for system-level ESD simulations.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk, ANSYS Totem, ANSYS PathFinder
Industry: Aerospace and Defense, Automotive, Consumer Products, High Tech
Sub Industry: Semiconductor Design, Semiconductors


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Ensuring Power & Noise Reliabilty of your High Performance SoCs with ANSYS RedHawk Analysis Software - Webinar

In globally competitive markets for mobile, consumer, automotive and networking, the success of high performance SoCs relies upon power efficiency, performance and reliability. During this webinar you will learn about how ANSYS RedHawk, the most trusted, industry-standard power integrity and reliability solution, enables designers to preserve the integrity of the power delivery network and accurately predict power and noise for the most advanced, high performance SoCs from chip to package to board. We will also demonstrate thermal-aware EM analysis, chip-package-system cosimulation, SoC ESD integrity verification, and timing (clock, critical path) impact analysis.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk
Product Category: Electronics


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ANSYS 18 Innovations - Electronics Cooling

ANSYS 18 delivers innovative new solutions for electronics cooling. Thermal integrity is a critical design consideration for enclosure design, packages, and PCBs that affect reliability and product lifecycle. Thermal impact on the package, especially from the IC, is a key driver for material selection, cooling and form factor decisions that ultimately determine the size, weight and cost of the final product. It is critical for package and system designers to determine the thermal signature of their system.

Attend this webinar to learn about important new capabilities in ANSYS 18 regarding electronics cooling simulation, such as importing chip thermal models (CTM) from ANSYS RedHawk to ANSYS Icepak for thermal analysis of the complete IC, package and PCB. Designers of high-speed digital electronics, and thermal and mechanical engineers involved in electronic design should attend this informative webinar on electronics cooling analysis.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk, ANSYS Icepak


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Power Noise and Reliability Analysis on Multi-Gigabit SerDes Interface IP - Webinar

This webinar covers ways and methods to ensure power noise integrity and reliability of multi-gigabit SerDes chip designs using ANSYS solutions.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem, ANSYS PathFinder, ANSYS RedHawk


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Power Noise Closure With Up to 10x Total Productivity Gain for Advanced Networking ASICs - Webinar

Challenges routinely faced by networking chip designers include extremely big capacity due to growing complexity of chips; more accurate modeling of the system and co-analysis at the top-level; chip thermal solution for chip power systems; comprehensive coverage of different modes of analysis in power integrity check; and timing impact annotation for jitter analysis and timing closure, just to name a few.

Join us for this webinar and discover how ANSYS RedHawk can help you to meet these challenges, with a focus on power integrity and reliability of advanced networking application-specific integrated circuits (ASICs). Learn how RedHawk’s capabilities in DMP (distributed machine processing), CPA (chip package analysis), CTA (chip thermal analysis) and thermal-aware EM (electromigration) analyses can provide a total productivity gain of up to 10x in networking chip design.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk


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Best Practices on Mitigating the Challenges of Power Noise Closure for Advanced FinFET Designs - Webinar

Presentation examines the latest features of RedHawk for FinFET designs.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk


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Thermal Integrity and Thermal-Aware EM Reliability Check for 3D Stacked Dies in EV-HEV - Webinar

Power and performance are key requirements for EV/HEV. The electronics in a modern automobile must operate in a high temperature environment — such as under the hood — without sacrificing performance. Thermal integrity and thermal-aware reliability are some of the biggest concerns that can affect power (leakage), IR, timing and electromigration (EM).

Learn how Freescale uses ANSYS RedHawk, SIwave, and Sentinel-TI to design 3-D stacked dies (memory on top of SoC) that can improve power consumption and channel communication speed, while mitigating thermal interaction and reliability issues. Discover how Freescale’s model-based thermal-aware power noise and reliability methodology can help you improve your 3-D stacked die design.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Sentinel, ANSYS SIwave, ANSYS RedHawk
Industry: Automotive


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Noise Coupling Analysis for Advanced Mixed-signal IC's - Webinar

Jacob Bakker, Sr. Design Methodology Engineer at NXP will discuss the challenges and their experience in achieving interference-free operation when integrating multiple RF and analog functions on a single RF-CMOS chip. The chip is part of NXP's SAF360X platform, and replaced six chips, which together enabled the three major digital terrestrial radio standards that covers the world. Jacob will also discuss the effective use of ANSYS RedHawk and Totem platforms to achieve the required interference-free operation.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS Totem, ANSYS RedHawk
Product Category: Electronics - Electromechanical


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How to Use RedHawk 2014 for Power Noise and Reliability Sign-off of FinFET Based Designs

This webinar covers new capabilities in RedHawk 2014 that enable power noise and reliability sign-off for large FinFET based designs with the same accuracy as “flat” simulation. The key capabilities covered are: - Distributed Machine Processing (DMP) - Chip-Package Co-Analysis (RedHawk-CPA) - Temperature-aware EM methodology

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS RedHawk
Product Category: Electronics - Electromechanical
Industry: High Tech
Sub Industry: A and D Electronics, Consumer Electronics


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