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ANSYS in ACTION: Enabling FinFET Thermal Reliability Signoff for IPs - Webinar

ANSYS Totem can solve the challenges faced by engineers trying to ensure thermal and electromigration (EM) reliability in advanced IPs. View this webinar to see a demonstration of self-heat analysis on an IP test case using ANSYS Totem’s rich GUI interface. The demonstration will cover flow setup, debugging and result exploration for reliability signoff.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Product Category: Electronics


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Enabling Power and Reliability Signoff for AMS Designs - Webinar

View this webinar to learn how ANSYS Totem can model and simulate the required power and reliability signoff checks for AMS designs. This presentation will demonstrate the benefits of using Totem to perform dynamic voltage drop and EM checks through its rich GUI interface, which can also be leveraged for debugging purposes.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Product Category: Electronics
Sub Industry: Electrical and Electronics


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ANSYS in ACTION: Enabling Early Power and Reliability Analysis for AMS Designs - Webinar

View this webinar to discover the benefits of doing early power and reliability analysis with just a GDS layout. This presentation will demonstrate early IP level connectivity checks; missing via checks; point to point resistance and short path resistance checks; and early static analysis to identify structural design weaknesses using ANSYS Totem’s rich GUI interface.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Product Category: Electronics


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ANSYS in ACTION: Analog and Mixed Signal Workflows for Power and Reliability Signoff for SerDes IP and PMIC - Webinar

Analog and mixed signal IPs are very complex and require significant time to design, verify and validate. With increasing mask costs and tighter design cycles, first time silicon success is key to accelerate time to market and beat the competition. Watch this 20-minute webinar to learn how AMS workflows based on ANSYS Totem, a layout-based transistor level power and reliability signoff platform, can enable you to design the next generation of SerDes IP or PMIC for cutting-edge applications.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Sub Industry: Semiconductors


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Thermal, EM and ESD Reliability Signoff for Next Generation FinFET Designs - Webinar

This webinar highlights the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs. Providing high reliability is critical for next-generation automotive, mobile and high-performance computing applications; it can be addressed in a systematic way using ANSYS reliability platforms throughout the design cycle.

Learn how ANSYS solutions offer comprehensive chip-package-system thermal analysis, as well as thermal aware EM sign-off, for finFET designs. Discover how ANSYS PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for human body model (HBM) and charged device model (CDM) analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and generating SoC-level ESD models for system-level ESD simulations.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk, ANSYS Totem, ANSYS PathFinder
Industry: Aerospace and Defense, Automotive, Consumer Products, High Tech
Sub Industry: Semiconductor Design, Semiconductors


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Using ANSYS Totem to Ensure Power and Noise Integrity of High Performance Analog and Mixed-signal Designs - Webinar

Learn why all major semiconductor companies use Totem for sign-off in their production flow to achieve stringent power noise and reliability requirement for their mixed-signal IP, analog and custom-IC designs, and how Totem is the only solution today that can analyse complex mixed-signal blocks containing both analog and digital content.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Product Category: Electronics
Sub Industry: Semiconductors


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Designing Reliable Power Management ICs: Tips and Tricks - Webinar

Power management is crucial in electronic systems to ensure that valuable power resources are not wasted unnecessarily. Electronic device users place a premium on increasing the time between battery recharging. ANSYS Totem can help you to optimize your design to ensure the reliability for your power management ICs (PMICs).

Attend this webinar to learn about simulation techniques related to resistance and current density. Discover how to use Totem to detect weak areas of a design at different levels and phases of power management design – from PMIC module or IP, to its integration at the full chip level.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem


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Power Noise and Reliability Analysis on Multi-Gigabit SerDes Interface IP - Webinar

This webinar covers ways and methods to ensure power noise integrity and reliability of multi-gigabit SerDes chip designs using ANSYS solutions.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem, ANSYS PathFinder, ANSYS RedHawk


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Fast and Effective Analysis for Power Management ICs - Webinar

Through this webinar learn how Totem can be used as a comprehensive simulation platform for voltage drop, reliability (EM/ESD) and noise coupling analyses of full-chip analog, mixed-signal I/O designs. Discover how Totem enables comprehensive power integrity and reliability verification of PMICs by using checks, such as resistance and current density, for detecting weak areas of a design - not only during the design phase of a PMIC module or IP, but also during its integration at the full chip level.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem
Industry: Automotive
Sub Industry: Car and Light Truck OEMs, Mobile Computing


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Power Noise and Reliability of High Speed IO Designs - Webinar

ANSYS Totem provides a comprehensive simulation framework for voltage drop, reliability (EM/ESD) and noise coupling analyses of analog, mixed-signal I/O designs. Modern chip manufacturers use engineering simulation to gain confidence in their designs and to help speed their new products to market.

Learn how Totem analyzes static and dynamic voltage drop at the IP or full-chip level to verify IP, not only during the design phase, but also during its integration at the SoC-level. Discover how Totem can validate your high-speed parallel I/O interfaces by simulating the complete I/O bank — together with the entire power distribution network for on-die, package, and PCB — to predict the effect of simultaneous switching noise (SSN) on signal transmission and on-chip jitter.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS Totem


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