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A Model-based Safety Flow for Automotive Semiconductor Products in Battery Management Applications

Because they are tiny and virtually invisible, it’s easy to overlook the central importance of the semiconductors that underlie reliable automotive performance today. But these small systems allow larger electronics networks to control every aspect of a car’s performance — including the batteries that drive many of the critical systems in the vehicle.

In this webinar, NXP engineers present their work on a model-based flow to develop safety-related automotive semiconductor products using ANSYS medini for semiconductors. Attend this event to learn how a seamless top-down methodology helps NXP engineers handle demanding safety challenges. It enables a consistent integration of all safety deliverables from safety goals down to the architecture as well as extensive safety analysis. NXP presenters will use an automotive battery management IC as an example to describe the challenges and the individual flow steps.

Author: ANSYS, Inc. Type: Webinar Date:
Product Category: Semiconductors
Industry: Automotive


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Elastic Compute Scalable Design Methodologies for Next-Generation FPGAs

Next-generation field programmable gate arrays (FPGAs) for 5G, AI, automotive, cloud and data center applications are getting bigger, faster and more complex. With the market’s continuous demand for higher performance and lower power products, FPGA designers strive hard to achieve stringent power, performance, area and reliability goals to stay ahead of the game. Traditional electronic design automation (EDA) techniques for full-chip critical path timing analysis and power integrity signoff cannot meet the capacity, performance and accuracy requirements for these complex FPGAs. Productivity and project schedules are negatively impacted as a result.

In this webinar, FPGA inventor Xilinx discusses the many applications for its innovative elastic compute scalable design methodologies, including:

  • Large design scaling for timing analysis using ANSYS SeaScape
  • Full-chip EM/IR signoff using ANSYS RedHawk-SC
  • Accelerated chip-scale interconnect delay calculation for timing capture flow using ANSYS Path FX

Author: ANSYS, Inc. Type: Webinar Date:
Product Category: Semiconductors, Cloud and IT Solutions
Industry: Automotive


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Leveraging Chip Power Models for System-Level EMC Simulation of Automotive ICs

The design of integrated circuits (ICs) for electromagnetic compatibility (EMC) is a fundamental requirement for the security and safety of automotive electronics systems. These must be tested for noise emission, electromagnetic interference (EMI) and for electromagnetic susceptibility (EMS) with intentional radio frequency (RF) disturbance. To achieve safety goals, chip power model (CPM) simulation is extended to evaluate the creation of noise from ICs and to capture the response of ICs to RF disturbance. This is done by leveraging the ANSYS chip ESD compact model (CECM) that captures the snapback current-voltage transfer characteristics of the ESD protection devices, silicon substrate coupling around the devices and also the chip-package-printed circuit board (PCB) interaction. The measurements and simulation are demonstrated with silicon test chips.

In this on-demand webinar,  Karthik Srinivasan, senior product manager from ANSYS and Dr. Makoto Nagata from Kobe University, Japan, will demonstrate how integrated circuit (IC), package and board designers can leverage ANSYS chip models in system-level simulations to meet the strict EMC requirements.

Author: ANSYS, Inc Type: Webinar Date:
Product Category: Semiconductors
Industry: Automotive


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Addressing Multiphysics Challenges in 7nm FinFET Designs

Variability has become the new enemy in 7nm FinFET designs. You can’t fix what you can’t find, and variability takes many forms (e.g., voltage drop, temperature, process). Increased cross-coupling of various multiphysics effects such as timing, power and thermal in 7nm designs poses significant challenges for design closure. Traditional solutions using margin-based methodologies are inadequate. Increased variability makes it hard to predict true silicon behavior and impacts both time-to- result (TTR) and time-to-market (TTM) goals in complex design projects.

View this on-demand webinar to learn how ANSYS multiphysics simulations can address the different forms of variability and their impact on performance. With an understanding of the true limits of built-in margins, you can achieve the target maximum frequency on silicon, while drastically improving the functional yield of your chips.

Author: ANSYS Type: Webinar Date:
Product Category: Semiconductors


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High Coverage, Multivariable Build Quality Metrics in Power Integrity Signoff

The availability of ubiquitous data and compute power to solve seemingly unsolvable problems is driving the artificial intelligence (AI) revolution in high tech today. Semiconductor chips for next-generation automotive, mobile and high-performance computing applications — powered by AI and machine learning algorithms — require the use of advanced 16/7nm systems-on-chips (SoCs), which are bigger, faster and more complex. For these SoCs, the margins are smaller, schedules are tighter and costs are higher. Faster convergence with exhaustive coverage is therefore imperative for first-time silicon success. A big data-enabled simulation platform that offers elastic scalability is required for enabling rapid design iterations to create a robust power grid design. Multivariable analytics and machine learning technologies are key for gaining valuable insights from the vast amount of simulation data to accelerate design closure.

In this on-demand webinar, leading semiconductor company Nvidia will discuss the limitations of traditional voltage drop analysis methodologies and share how ANSYS RedHawk-SC’s elastic compute scalability and powerful data analytics can be leveraged to accelerate next-generation SoC power integrity and reliability signoff. A new workflow using multivariable analytics, which considers grid criticality, timing criticality and simultaneous switching noise, is used for predicting the worst, local dynamic voltage drop (DvD) hotspots without running any transient simulation. This enables early detection of hotspots and offers feedback to the physical design team, making it possible to address design issues without impacting the tapeout schedule. The issues identified by this new flow were found to correlate well with vector-based dynamic voltage drop analysis with much faster turnaround time.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS RedHawk
Product Category: Semiconductors
Sub Industry: Semiconductor Design, Semiconductors


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Differential Energy Analysis for Improved Performance/Watt in Mobile GPU

Mobile devices demand high performance in a very constrained environment. As a leader in perf/watt, Qualcomm® Adreno™ GPUs, a product of Qualcomm Technologies, Inc., leverages many effective methods to improve power efficiency. In this regard, Qualcomm has developed a differential energy analysis methodology based on ANSYS PowerArtist to identify the power optimization opportunity in GPU. This methodology can help to locate the inefficient part that needs further optimization in the pre-silicon stage. Experimental results based on identifying unnecessary register toggles demonstrate the effectiveness of this proposed methodology. View this on-demand webinar to learn more.

Speakers: 
Preeti Gupta, is head of RTL product management, for the ANSYS semiconductor business unit.

Yadong Wang is currently a staff engineer in the GPU system power team at Qualcomm Technologies, Inc., San Diego, California. He has about 10 years of ASIC low-power design experience. At Qualcomm, he is responsible for power modeling and analysis of Adreno™ GPUs, and explores and develops many effective methods to improve power efficiency. Before joining Qualcomm, he worked as a hardware power engineer at NVIDIA. Yadong earned an M.S. degree in electrical engineering from Tongji University (Shanghai, China) in 2009.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS PowerArtist
Product Category: Semiconductors
Industry: High Tech
Sub Industry: Semiconductor Design, Semiconductors


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Winning in the Digital Economy - Engineering Smart, Connected Products, Operations and Services - Webinar

The digital economy presents a unique, never-before opportunity to connect humanity. The Internet of Things (IoT) and digital technologies (e.g., digital twins) are revolutionizing nearly every industry imaginable, and personalized healthcare, connected cars and wearable electronics are just a few of the many applications. Engineering simulation provides a competitive edge for companies looking to develop better products – faster.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS HFSS
Product Category: Electronics - Electromechanical, Electronics - High Frequency Electromagnetics, Electronics - Integrated Circuits, Electronics - Signal Integrity, Embedded Software, Electronics, Semiconductors
Industry: Healthcare - BioMed, High Tech, Consumer Products, Automotive
Sub Industry: Biomedical Devices, Computer and Storage Devices, Consumer Electronics, Diagnosis and Personalized Medicine, Electrical and Electronics, Household Goods, Mobile Computing


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Designing Power-Efficient RTL for IoT Chips - Webinar

Within a few years we will be living in a smart world powered by billions of IoT (Internet of Things) devices. To be efficient, these devices will have to be energy-smart. This requires making the right decisions early in the design process to impact the power consumption of IoT semiconductor chips.

Learn how the RTL hardware description language delivers predictable accuracy that enables early power-related design decisions. Discover how a low-power methodology can make RTL energy-efficient for IoT applications by focusing on power analysis, power reduction and power regressions.

Author: ANSYS Type: Webinar Date:
Product Category: Semiconductors
Sub Industry: Semiconductor Design


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