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Challenges and Trends in SoC Electromagnetic (EM) Crosstalk

Electromagnetic Crosstalk analysis is emerging as a fundamental necessity as a component of electronic system development. With the advent of advanced technologies and System on-Chip (SoC) architectures, ignoring electromagnetic crosstalk is highly risky resulting in significant delays in reaching the market on time as well significant cost over runs. This paper provides an overview of the state of the practice in electromagnetic crosstalk in the context of modern SoC designs, current industrial trends, and key adoption challenges.

Author: ANSYS, Inc. Type: White Paper Date:
Product Name: ANSYS RaptorX, ANSYS Pharos, ANSYS Exalto, ANSYS VeloceRF
Product Category: Semiconductors


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Multiphysics Simulations for AI Silicon to System Success

Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed design methodologies with multiphysics simulations and multi variable analytics to exceed PPA and reliability goals. ANSYS brings together the power of big data analytics, elastic compute scalability and multiphysics simulations to simultaneously address power, thermal, variability, timing, electromagnetics and reliability challenges across the spectrum of chip, package and system to promote first time silicon to system success.

Author: ANSYS, Inc. Type: White Paper Date:
Product Category: Semiconductors


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Multiphysics Reliability Signoff for Next-Generation Automotive Electronics Systems

Automotive electronics systems depend on an ever-increasing number of electronic sensors and processing elements, which allow for 360-degree surveillance and object identification/classification. Designing and verifying these systems is, however, as complex as the systems themselves.

This white paper examines how automotive chip designers can achieve the stringent safety and reliability requirements for advanced FinFET designs. It explores analysis solutions for electromigration reliability (EM), electrostatic discharge (ESD), thermal reliability, statistical electromigration budgeting (SEB) and functional safety.

Author: ANSYS, Inc. Type: White Paper Date:
Product Category: Semiconductors, Multiphysics
Industry: Automotive


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Differential Energy Analysis to Optimize Mobile GPU Power

Operating power has become one of the most important metrics for modern electronic devices. Qualcomm Technologies, a world-class mobile solution provider, significantly reduced power consumption in an already challenging market by performing power analysis at RTL using ANSYS PowerArtist. Qualcomm Technologies was able to reduce dynamic power by 10 percent through this approach.

Author: ANSYS Inc. Type: White Paper Date:
Product Name: ANSYS PowerArtist, ANSYS RedHawk
Product Category: Semiconductors
Sub Industry: Electrical and Electronics


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系统感知型SoC的功耗、噪声和可靠性验收

在全球竞争激烈的移动、消费类和汽车电子系统市场中,低功耗、高性能以及高可靠性是至关重要的成功因素。为了应对这些相互冲突的要求,设计团队需要面面俱到地考虑多种方案,例如采用高级工艺技术节点,尤其是基于FinFET的器件。这些高级技术节点让芯片不仅能在更低功耗下以更快的速度运行,同时还可在相同尺寸的硅片中集成更多功能。但是,在这些工艺节点上,由于器件的物理特性、尺寸和形状以及互联等因素,在进行功耗、噪声和可靠性验收时会遇到严重问题。

Author: ANSYS Type: White Paper Date:
Product Name: ANSYS RedHawk
Product Category: Semiconductors
Industry: High Tech


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低功耗设计方法助力尽早实现功耗收敛

商用功耗分析工具推出已十年有余,主要应用在门级和晶体管级的抽象层面上。对模拟、混合信号和定制设计来说,晶体管级的工具既可当作设计工具使用,也可当作验证工具使用。它们可帮助设计人员分析功耗,并能作为最终“验收”工具使用,以确保满足功耗规格。在综合驱动的基于标准单元的ASIC和SoC设计上,门级和晶体管级功耗分析工具一般都作为最终验证工具使用。如果在验证过程中发现有要求重新综合设计的强制性设计修改,那么就需要进入广泛的验证阶段了。由于在流程中需要使用多种工具进行多次迭代,这样就会导致更长的设计收敛时间。本白皮书将介绍一种低功耗设计(DFP)方法,它从设计流程的寄存器传输级(RTL)阶段开始,旨在满足设计的功耗预算以及设计收敛时间和产品上市时间的要求。

Author: ANSYS Type: White Paper Date:
Product Name: ANSYS PowerArtist
Product Category: Semiconductors
Industry: Construction
Sub Industry: Semiconductors


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使用ANSYS RedHawk-CPA进行芯片封装协同分析

ANSYS RedHawk-CPA是一款集成型芯片封装协同分析解决方案,其可利用ANSYS RedHawk实现快速准确的封装布局建模,充分满足片上电源的完整性仿真需求。有了RedHawk-CPA,设计人员可分别遵循Redhawk的静态和动态分析,来执行封装布局的静态IR压降分析和AC热点分析。

Author: ANSYS Type: White Paper Date:
Product Name: ANSYS RedHawk
Product Category: Semiconductors
Industry: High Tech
Sub Industry: Semiconductor Design


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Early Power Closure Using a Design for Power Methodology - White Paper

A whitepaper on RTL power analysis, estimation and optimization using ANSYS PowerArtist.

Author: ANSYS, Inc. Type: White Paper Date:
Product Name: ANSYS PowerArtist
Product Category: Semiconductors
Industry: Automotive, Healthcare - BioMed
Sub Industry: Mobile Computing


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A Methodology for Comprehensive and Productive Power Noise and Reliability Closure for Advanced SoC Designs - White Paper

One of the key technology trends driving the semiconductor industry is the adoption of FinFET processes. As opposed to a traditional planar transistor, the FinFET has an elevated channel or 'fin', which the gate wraps around. Due to their structure, FinFETs consume much lower leakage power and allow greater device density. Compared to planar transistors, FinFETs operate at a lower voltage and offer higher drive current. All of these properties lead to lower circuit delay, lower leakage and higher performance packed into a smaller area. This also means that FinFETs offer reduced cost per unit performance. Designing a complex SoC using advanced FinFET-based technologies for first pass silicon success requires proven tools and methodology.

Author: ANSYS, Inc. Type: White Paper Date:
Product Name: ANSYS RedHawk
Product Category: Semiconductors
Industry: High Tech


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Chip-Package Co-analysis Using ANSYS RedHawk-CPA - White Paper

ANSYS RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using ANSYS RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliable supply of power, and stable voltage levels at the transistor connection points, the entire system power delivery network (PDN) must be optimized and validated, including the impact of package on a chip.

Author: ANSYS, Inc. Type: White Paper Date:
Product Name: ANSYS RedHawk
Product Category: Semiconductors
Industry: Automotive, High Tech


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