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Differential Energy Analysis for Improved Performance/Watt in Mobile GPU

Mobile devices demand high performance in a very constrained environment. As a leader in perf/watt, Qualcomm® Adreno™ GPUs, a product of Qualcomm Technologies, Inc., leverages many effective methods to improve power efficiency. In this regard, Qualcomm has developed a differential energy analysis methodology based on ANSYS PowerArtist to identify the power optimization opportunity in GPU. This methodology can help to locate the inefficient part that needs further optimization in the pre-silicon stage. Experimental results based on identifying unnecessary register toggles demonstrate the effectiveness of this proposed methodology. View this on-demand webinar to learn more.

Speakers: 
Preeti Gupta, is head of RTL product management, for the ANSYS semiconductor business unit.

Yadong Wang is currently a staff engineer in the GPU system power team at Qualcomm Technologies, Inc., San Diego, California. He has about 10 years of ASIC low-power design experience. At Qualcomm, he is responsible for power modeling and analysis of Adreno™ GPUs, and explores and develops many effective methods to improve power efficiency. Before joining Qualcomm, he worked as a hardware power engineer at NVIDIA. Yadong earned an M.S. degree in electrical engineering from Tongji University (Shanghai, China) in 2009.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS PowerArtist
Product Category: Semiconductors
Industry: High Tech
Sub Industry: Semiconductor Design, Semiconductors


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How ANSYS PowerArtist Helps Achieve Your Power Budget for Power Efficient Semiconductor Design - Webinar

Power and energy efficiency are paramount in semiconductor design for applications from mobile to CPU to networking to automotive ICs. ANSYS PowerArtist is a comprehensive RTL design-for-power platform with the ability to analyze, debug and reduce power for all of these semiconductor designs.

This webinar will demonstrate how PowerArtist can model physical effects to achieve predictable RTL power accuracy enabling early design decisions with confidence. Learn how PowerArtist identifies block- and instance-level sequential and combinational power reduction opportunities across the clock network, datapath and memory architectures reducing power by up to 70%. We will also show how power profiling, running 1000X faster than traditional temporal power analyses, can help you analyze system level use cases early in the design flow.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS PowerArtist
Industry: Energy
Sub Industry: Semiconductors


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Optimizing Processor Power-to-Performance Ratios Using Early RTL Design-for-Power Methodology - Webinar

Conventional approaches for chip power-consumption analysis begin once a gate level netlist is available. At this stage, possible changes that can impact power are limited by schedule and cost considerations. AMD recently adopted ANSYS PowerArtist for a design-for-power methodology that begins early at the RTL stage, making it possible to significantly reduce power consumption on a processor design.

Learn how, through rigorous tracking of power over multiple bandwidth scenarios, AMD identified areas of significant wasted power consumption and addressed them through high-impact RTL changes. Discover how they achieved a 70 percent power reduction in the idle mode and an improvement of 400 percent in the power-bandwidth slope using ANSYS PowerArtist.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS PowerArtist


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Radio Interference Reduction of Digital Logic for Automotive Infotainment Application by Low Power Optimization at RTL with ANSYS PowerArtist - Webinar

Integrating more and more functionality into a single die can cause noise interference when analog and digital components are placed close to each other. Effective devices must eliminate or minimize this interference, specifically in cases where noise from digital components negatively affects analog components.

In this webinar, Peter Blinzer from NXP Hamburg will present a new methodology to reduce noise interference from digital logic devices early in the design flow at the RTL level. Discover how he used the power analysis, debug and reduction capabilities of ANSYS PowerArtist to optimize the design of an automotive infotainment application.

Author: ANSYS Type: Webinar Date:
Product Name: ANSYS PowerArtist
Industry: Automotive


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PowerArtist for Early RTL Power Analysis and Reduction

PowerArtist is a complete RTL Design-for-Power platform with fully-integrated power analysis and automated reduction within a powerful graphical debug and Tcl-based regression framework. This presentation highlights PowerArtist’s PACE™ for modeling the physical design effects enabling predictable RTL accuracy and reliable power budgeting with 10X productivity over gate-level analysis. This presentation will also describe how PowerArtist’s RPM™ captures RTL power data for power-critical switching events enabling early and robust power grid planning.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS PowerArtist
Product Category: Electronics
Industry: High Tech


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Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications

Every new generation of a mobile IC has increased performance, lower power and smaller form factor requirements. Process migration and the shift to 3D-ICs have made the design of such ICs possible without making compromises. To achieve reliable operation of the IC within the context of the system, various aspects of power noise and reliability need to be validated.

● Early power analysis and prediction is mandatory to meet the demanding power efficiency targets
● Power integrity verification for sub-1V supply voltage levels to ensure performance at spec for all operating modes of the chip
● High-speed low-power I/Os such as LPDDRs must be verified with the impact of core and system noise to meet the stringent chip-to-chip communication jitter requirements
● Reliability verification such as Electromigration (EM) and Electrostatic Discharge (ESD) should be part of the design process for ICs manufactured using the most advanced process nodes
● Thermal reliability simulations must be performed at the system level to ensure thermal stability of high-performance die within small hand-held devices

This presentation will discuss the various aspects of designing Mobile and High Performance ICs for power and reliability using various ANSYS-Apache simulations platforms.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS PowerArtist, ANSYS Sentinel, ANSYS Totem, ANSYS RedHawk
Product Category: Electronics


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Power Noise Reliability Sign-off for Custom and Analog IPs with SoC Integration

Mixed-signal, analog, RF and discrete memory devices are increasingly complex, with the shift towards smaller technology nodes and higher levels of integration. Traditional correct-by-construction or Spice-based verifications cannot perform exhaustive layout-based checks that are necessary to ensure these custom design circuits operate properly for voltage drop, noise coupling, and reliability considerations - not only at an IP-level, but also at the SoC-level where they are increasingly utilized.

This presentation will outline ANSYS-Apache’s simulation technologies that address analysis needs for custom and analog IPs including static and dynamic voltage drop, power and signal line EM and ESD integrity sign-off. Additionally, it will demonstrate a full-chip SoC-level analysis flow that can model the noise coupling between high-speed digital and sensitive analog circuits through the silicon substrate, on-die metal power grid, or the shared package planes to help optimize guard ring design.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS PowerArtist, ANSYS Sentinel, ANSYS Totem, ANSYS PathFinder, ANSYS RedHawk
Product Category: Electronics
Industry: High Tech


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Chip-Package-Methodologies for Reliable, Cost-Optimized ICs for Automotive and Embedded Applications

The use of high-performance processors for Automotive and Embedded applications is continuing to rise. Unlike other applications, the ICs used for these markets must care about individual component-level power-performance-cost trade-offs in addition to compatibility with other IC’s and overall integration within a system environment. These types of designs must meet key targets such as Power Budgeting, Power Integrity, Electronic Interference Compatibility, Electric Discharge Immunity and Thermal susceptibility.

This presentation will explain how ANSYS-Apache technologies address Chip-Package-System analysis needs utilizing solutions such as PowerArtist, RedHawk, Totem, PathFinder, Sentinel and SIwave.

Author: ANSYS, Inc. Type: Webinar Date:
Product Name: ANSYS PowerArtist, ANSYS Sentinel, ANSYS Totem, ANSYS SIwave, ANSYS PathFinder, ANSYS RedHawk
Industry: Automotive, High Tech


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